Diagnosing the interconnect of bus-connected multi-RAM systems under restricted and general fault models

This paper presents new approaches for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short, open and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well as by the presence of memories (whose number is given by D). Detection and maximal diagnosis are considered under a restricted fault model (short faults only) as well as a general fault model (all types of faults).

[1]  W. Kent Fuchs,et al.  Optimal interconnect diagnosis of wiring networks , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Frank W. Angelotti,et al.  System level interconnect test in a tristate environment , 1993, Proceedings of IEEE International Test Conference - (ITC).

[3]  Fabrizio Lombardi,et al.  Fault detection and diagnosis of interconnects of random access memories , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[4]  Fabrizio Lombardi,et al.  Maximal diagnosis of interconnects of random access memories , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[5]  Adriaan J. de Lind van Wijngaarden,et al.  Memory interconnection test at board level , 1992, Proceedings International Test Conference 1992.

[6]  Jun Zhao,et al.  Adaptive approaches for fault detection and diagnosis of interconnects of random access memories , 1998, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. No.98TB100236).

[7]  Fabrizio Lombardi,et al.  Interconnect diagnosis of bus-connected multi-RAM systems , 1999, Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing.