A 0.9 V 1.5 mW continuous-time /spl Delta//spl Sigma/ modulator for WCDMA
暂无分享,去创建一个
A second-order continuous-time /spl Delta//spl Sigma/ modulator for a WCDMA RX is implemented with inverter-based OTAs, enabling operation at a voltage of 0.9 V. The OTAs are balanced by using CMFB. The modulator consumes only 1.5 mW and occupies 0.12 mm/sup 2/ in a 0.13 /spl mu/m CMOS process. SNDR is 50.9 dB over a bandwidth of 1.92 MHz.
[1] P. R. Gray,et al. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.
[2] Robert W. Adams,et al. Design and Implementation of an Audio 18-Bit Analog-to-Digital Converter Using Oversampling Techniques , 1986 .