Real-Time Connected Component Labeling on One-Dimensional Array Processors based on Content-Addressable Memory: Optimization and Implementation

Publisher Summary Connected component labeling is not easy to process because of its local and global features. These features make the labeling operation extremely time costly as sequential architecture has to be used because of its local operation principle. To reduce the processing time, labeling should be done in parallel using the local and global operations. This solution is very expensive, particularly for two- or three-dimensional array processors. To find a trade-off between processing time and hardware cost, this chapter proposes an efficient parallel architecture dedicated to connected component labeling based on content-addressable memory (CAM). For an n x n image, the optimized architecture merely requires n/2 -1 PEs and n 2 /4 CAM modules through a 4-pixels grouping technique. The algorithm proposed by the chapter, based on a divide-and-conquer technique, leads to a complexity of O(n log n) with a small multiplicative constant factor of an order of ½. The global communication is reconfigurable and ensured in O(log n) units of propagation time by a tree structure of switches. Hence, through this performance, this architecture reaches a quasi-optimal processor time in labeling. Moreover, the architecture permits sequential processing, perfectly adapted to labeling in one scan image from any interlaced-mode video signal.