A 7-ns/350-mW 64-kbit ECL-compatible RAM

A 7-ns 350-mW, 64-kbit ECL RAM was developed using 1.3-/spl mu/m high-performance bipolar-CMOS (Hi-BiCMOS) technology, in which a bipolar transistor of 7-GHz cutoff frequency is fabricated together with 1.3-/spl mu/m CMOS. A variable-impedance data-line load, a common data-line equalizing circuit, and a sense-amplifier selection technique together achieve a 7-ns access time. Gates combining bipolar and CMOS devices achieve a power dissipation of one-third that of conventional bipolar 64-kb ECL RAMs.

[1]  Masanori Odaka,et al.  A 13ns/500mW 64Kb ECL RAM , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  Peter W. Cook,et al.  A 15-ns CMOS 64K RAM , 1986 .

[3]  K. Uchibori,et al.  A 256K CMOS SRAM with variable-impedance loads , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  T. Ikeda,et al.  High speed BiCMOS VLSI technology with buried twin well structure , 1985, 1985 International Electron Devices Meeting.

[5]  T. Awaya,et al.  64Kb ECL RAM with redundancy , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  R. I. Kung,et al.  Two 64K CMOS SRAMs with 13ns access time , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.