Digital observer based current loop control for buck converters - Prototype implementation on an FPGA

This paper presents an approach for current sensing in digital controlled buck converters. From the several possible techniques for current sensing an observer based algorithm in a digital implementation is used as it has the advantage of not needing an additional sensor or shunt in the circuit which causes additional power losses and costs. The system concept used herein works without additional A/D-converters (ADC) besides these, which are already available in the system. By making use of this sensorless current mode (SCM) concept a current signal is obtained, which is fed to the current loop of the controller. The working principle of this current sensing technique is investigated with system level simulations in ScicosLab and with a prototype based on an FPGA implementation of the algorithm. The controller together with the observer algorithm to estimate the inductor current was written in VHDL and implemented on a Xilinx Spartan 6 FPGA with a Digilent Nexys 3 board. In the simulations a noise floor of Vpp = 20 mV (peak-to-peak voltage) is added to the measured signals in order to account for the always present noise in real world systems.