A High Speed 4 Megapixel Digital CMOS Sensor

We developed, fabricated and characterized a shuttered 4 Mpixel digital CMOS sensor running at the rate over 400 Frames/s. This paper discusses the pixel, the column ADC and the data readout architecture. The sensor delivers over 1.8 GPix/s of data at the maximum clock rate of 120 MHz. We also discuss the techniques implemented in the chip to reduce electronic noises. The closest published sensor is a 4 Mpixel sensor developed by Photobit Technology [1], and which has become a popular product to machine vision and motion capture industries. The chip reported here achieves better functionality (shutter replacing rolling shutter, 2X frame rate, less column f.p.n., less electronic noise) with different circuits. A simplified schematic of one column including the pixel, the column amplifier, and the ADC is drawn in Fig.1. The conventional 5T shutter pixel based on a regular (non-pinned) photodiode can not have good dark uniformity because the switches resetting the photodiode and the pixel memory have statistically different feedthrough. The responsivity of the pixel is reduced to approximately a half of the photodiode responsivity because of the charge sharing between the photodiode and the pixel memory. These disadvantages were addressed when designing a T-shape 5T shutter pixel which has a common reset switch for the photodiode and the memory, the solution that removes some of the fixed pattern noise. Responsivity was also improved almost twice because the pixel topology allows charge transfer rather than charge sharing. Implemented pixel was based on a traditional photodiode, so we observed some small-signal nonlinearity even when using flushing of the pixel. The non-linearity comes from the tail of the subthreshold current during the charge transfer through the transfer gate. An incomplete transfer should also give rise to the photodiode kTC noise. Implementing the photodiode as a pinned photodiode would improve the pixel linearity and should also remove this component of kTC noise. The column ADC implemented in the chip is of the successive-approximation type [2], same as of the prototype sensor [1], however it is built of different components. Instead of an offset-reduction calibration DAC in each column, the new ADC extensively uses auto-zeroing. To achieve both good f.p.n. suppression and short decision time (e.g. 10 ns), the autozeroing comparator is made of a 3-stage offsetcanceling pre-amplifier (similar to the one from reference [3]) and the reconfigurable dynamic latch which also uses an auto-zeroing for its offset reduction while in reset state. As a result, column f.p.n. was removed to the level non-detectable in the measurements. Instead, we started observing column f.p.n. from the source we did not expect before. The f.p.n. came from the ADC offset circuit generating the offset in each column with small area capacitor. The more bias is applied to the capacitor the more the offset is, and the more is the nonuniformity of the offset. During the ADC operation, the data is stored in column ADC registers. To increase the readout data rate from the registers, we split the readout into 4-quadrants (Fig.2.). Register bit lines and the data lines were