M-IVC: Applying multiple input vectors to co-optimize aging and leakage
暂无分享,去创建一个
[1] C.H. Kim,et al. An Analytical Model for Negative Bias Temperature Instability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[2] A. R. Newton,et al. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .
[3] Tao Li,et al. NBTI tolerant microarchitecture design in the presence of process variation , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[4] Shekhar Y. Borkar,et al. Design challenges of technology scaling , 1999, IEEE Micro.
[5] R. Rao,et al. A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits , 2003, ICCAD 2003.
[6] Zhenyu Qi,et al. NBTI resilient circuits using adaptive body biasing , 2008, GLSVLSI '08.
[7] Yu Cao,et al. New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.
[8] Edward J. McCluskey,et al. Probabilistic Treatment of General Combinational Networks , 1975, IEEE Transactions on Computers.
[9] Yu Cao,et al. The Impact of NBTI on the Performance of Combinational and Sequential Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[10] Yu Cao,et al. Predictive Modeling of the NBTI Effect for Reliable Design , 2006, IEEE Custom Integrated Circuits Conference 2006.
[11] Yu Wang,et al. Gate replacement techniques for simultaneous leakage and aging optimization , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[12] Yu Cao,et al. An efficient method to identify critical gates under circuit aging , 2007, ICCAD 2007.
[13] Vishwani D. Agrawal,et al. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.
[14] Yu Wang,et al. Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[15] Ku He,et al. Temperature-aware NBTI modeling and the impact of input vector control on performance degradation , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[16] Yu Wang,et al. Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[17] Yu Cao,et al. Modeling and minimization of PMOS NBTI effect for robust nanometer design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[18] Josep Torrellas,et al. Facelift: Hiding and slowing down aging in multicores , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[19] Feng Gao,et al. Exact and heuristic approaches to input vector control for leakage power reduction , 2004, ICCAD 2004.
[20] Josep Torrellas,et al. Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[21] Sachin S. Sapatnekar,et al. NBTI-Aware Synthesis of Digital Circuits , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[22] Jaume Abella,et al. Penelope: The NBTI-Aware Processor , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[23] K. Yamaguchi,et al. The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling , 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
[24] Massoud Pedram,et al. Leakage current reduction in CMOS VLSI circuits by input vector control , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[25] Yu Wang,et al. On the efficacy of input Vector Control to mitigate NBTI effects and leakage power , 2009, 2009 10th International Symposium on Quality Electronic Design.
[26] Scott A. Mahlke,et al. Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[27] Robert K. Brayton,et al. A new algorithm for statistical circuit design based on quasi-newton methods and function splitting , 1979 .