论文信息 - Programmable quasi-passive algorithmic digital- analogue converter

Programmable quasi-passive algorithmic digital- analogue converter

Abstract A digital-to-analogue converter circuit is presented which employs a quasi-passive, parasitic-compensated, switched- capacitor circuit to implement a conversion algorithm consisting of a charge division between equal-valued capacitors. Both the conversion speed and resolution can be programmed by digital means to suit a wide variety of low-cost applications with conversion rates up into the megahertz range. The analogue portion of the converter has been integrated using a 2·5 μm CMOS double-poly technology and occupies a mere 0·25 mm2. The results of the experimental evaluation of some sample prototype chips are presented and analysed.

J. E. Franca | J. C. Vital

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