Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit

In burst transmission systems such as passive optical networks (PONs), a burst-mode CDR circuit must be able to retime and reshape the input data. In this paper, a burst-mode CDR circuit is presented that achieves output-data-jitter reduction of 3dB at jitter frequency of 1GHz, synchronization to the input data within 14 bits of the burst input, and tolerance to pulse-width distortion (PWD) of +0.22/−0.32UI at 10.3125Gb/s operation. These characteristics are provided by a CDR architecture with jitter-reduction and PWD-compensation circuits.