Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit
暂无分享,去创建一个
Jun Terada | Naoto Yoshimoto | Hiroaki Katsurai | Kazuyoshi Nishimura | Shunji Kimura | Yusuke Ohtomo | S. Kimura | N. Yoshimoto | K. Nishimura | Y. Ohtomo | J. Terada | Hiroaki Katsurai
[1] Jri Lee,et al. A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique , 2008, IEEE Journal of Solid-State Circuits.