CMOS IC fault models, physical defect coverage, and I/sub DDQ/ testing

The development of the stuck-at fault (SAF) model is reviewed with emphasis on its relationship to CMOS integrated circuit (IC) technologies. The ability of the SAF model to represent common physical defects in CMOS ICs is evaluated. A test strategy for defect detection, which includes I/sub DDQ/ testing, is presented.<<ETX>>

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