A parallel implementation of large-scale circuit simulation

An efficient hierarchical parallel implementation of LSI circuit simulation is presented. The block Gauss-Seidel waveform relaxation algorithm is adopted as the first-level parallel computation and is combined with the second-level pipelining and parallel schemes in the various phases of a direct analysis of each subcircuit. Experimental results demonstrating the effective parallelism and the time cost reduction by the proposed methods are presented.<<ETX>>