Energy-efficient, decision feedback equalization Using SAR-like capacitive charge summation

A capacitive charge-sharing, decision feedback equalization (DFE) circuit is presented for use in high-speed serial link receivers. Similar to the capacitive DAC (digital-analog converters) used in successive approximation-based ADCs (analog-digital converters), the proposed one-tap DFE with half-rate quantizer demultipliexing operates at 4Gbps, consuming 0.32 mW from a 1-V supply, excluding clock power. The proposed architecture, scalable to a large number of filter taps, shows considerable advantage in regards to energy efficiency over conventional, current-switched structures.

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