On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

The availability of quantum microprocessors is mandatory, to efficiently run those quantum algorithms promising a radical leap forward in computation capability. Silicon-based nanostructured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthesize control signals for spintronic qubits. In a quantum microprocessor, these circuits should operate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been systematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physical models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guidelines for the VCO/FD interface, useful in the absence of cryogenic DKs.

[1]  Dixian Zhao,et al.  Geometric Analysis and Systematic Design of Millimeter-Wave Low-Power Frequency Dividers in 65-nm CMOS , 2020, IEEE Access.

[2]  Myounggon Kang,et al.  Extraction and modeling of gate electrode resistance in rf MOSFETs , 2005, 2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005..

[3]  K. Itoh,et al.  Operation of a silicon quantum processor unit cell above one kelvin , 2019, Nature.

[4]  Esteban Tlelo-Cuautle,et al.  Single-Objective Optimization of a CMOS VCO Considering PVT and Monte Carlo Simulations , 2020, Mathematical and Computational Applications.

[5]  Arnout Beckers,et al.  Cryogenic MOS Transistor Model , 2018, IEEE Transactions on Electron Devices.

[6]  Arnout Beckers,et al.  A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics , 2019, 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems".

[7]  Michelle Y. Simmons,et al.  Silicon quantum electronics , 2012, 1206.5202.

[8]  Bo Lojek,et al.  History of semiconductor engineering , 2007 .

[9]  M. Peckerar,et al.  Compact modeling of 0.35µm SOI CMOS technology node for 4K DC operation using Verilog-A , 2010 .

[10]  C. R. Viswanathan,et al.  Low frequency noise in CMOSTs at cryogenic temperatures , 1989, Proceedings of the Workshop on Low Temperature Semiconductor Electronics,.

[11]  N. Arora.  MOSFET Models for VLSI Circuit Simulation , 1993 .

[12]  G. Burkard,et al.  Three-electron spin qubits , 2016, Journal of physics. Condensed matter : an Institute of Physics journal.

[13]  B. E. Kane.  A silicon-based nuclear spin quantum computer , 1998, Nature.

[14]  B. Razavi.  Design of CMOS Phase-Locked Loops , 2020 .

[15]  Christian Grewing,et al.  Systems Engineering of Cryogenic CMOS Electronics for Scalable Quantum Computers , 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

[16]  Torsten Lehmann,et al.  Cryogenic Support Circuits and Systems for Silicon Quantum Computers , 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

[17]  K. Itoh,et al.  Operation of a silicon quantum processor unit cell above one kelvin , 2020, Nature.

[18]  Edoardo Charbon,et al.  The electronic interface for quantum processors , 2018, Microprocess. Microsystems.

[19]  M. Veldhorst,et al.  Universal quantum logic in hot silicon qubits , 2019, Nature.

[21]  M. Vinet,et al.  Towards scalable quantum computing based on silicon spin , 2019, 2019 Symposium on VLSI Technology.

[22]  Edoardo Charbon,et al.  A Fully-Integrated 40-nm 5-6.5 GHz Cryo-CMOS System-on-Chip with I/Q Receiver and Frequency Synthesizer for Scalable Multiplexed Readout of Quantum Dots , 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).

[23]  Edoardo Charbon,et al.  A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons , 2020, IEEE Journal of Solid-State Circuits.

[24]  E. Charbon,et al.  Characterization and Modeling of Mismatch in Cryo-CMOS , 2020, IEEE Journal of the Electron Devices Society.

[25]  C. E. Hopper,et al.  Noise performance of 0.35-/spl mu/m SOI CMOS devices and micropower preamplifier from 77-400 K , 2004, IEEE Aerospace Conference. Proceedings.

[26]  Yan Wang,et al.  Behavioral Analysis and Optimization of CMOS CML Dividers for Millimeter-Wave Applications , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[27]  Alak Majumder,et al.  A 90nm PVT Tolerant Current Mode Frequency Divider with Wide Locking Range , 2020, 2020 IEEE Nordic Circuits and Systems Conference (NorCAS).

[28]  M. Veldhorst,et al.  Silicon CMOS architecture for a spin-based quantum computer , 2016, Nature Communications.

[30]  R. Mansour,et al.  Design Considerations for Spin Readout Amplifiers in Monolithically Integrated Semiconductor Quantum Processors , 2019, 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).

[31]  Arnout Beckers,et al.  Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K , 2018, IEEE Journal of the Electron Devices Society.

[32]  Yeong-Her Wang,et al.  A Current-Mode-Logic-Based Frequency Divider with Ultra-Wideband and Octet Phases , 2018 .

[33]  Edoardo Charbon,et al.  Benefits and Challenges of Designing Cryogenic CMOS RF Circuits for Quantum Computers , 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

[34]  D. E. Savage,et al.  A programmable two-qubit quantum processor in silicon , 2017, Nature.

[35]  D. Deutsch.  Quantum theory, the Church–Turing principle and the universal quantum computer , 1985, Proceedings of the Royal Society of London. A. Mathematical and Physical Sciences.

[36]  Michael Green,et al.  Dynamics of high-frequency CMOS dividers , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[37]  Yu Chen,et al.  29.1 A 28nm Bulk-CMOS 4-to-8GHz ¡2mW Cryogenic Pulse Modulator for Scalable Quantum Computing , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

[38]  P. Bertet,et al.  Donor Spins in Silicon for Quantum Technologies , 2020, Advanced Quantum Technologies.

[39]  A. Abidi,et al.  Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures , 1994 .

[40]  Lin Song,et al.  15.5 Cryo-CMOS circuits and systems for scalable quantum computing , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[41]  Eddy Simoen,et al.  Model for hysteresis and kink behavior of MOS transistors operating at 4.2 K , 1988 .

[42]  Edoardo Charbon,et al.  Characterization and Analysis of On-Chip Microwave Passive Components at Cryogenic Temperatures , 2020, IEEE Journal of the Electron Devices Society.

[43]  Edoardo Charbon,et al.  Cryo-CMOS Circuits and Systems for Quantum Computing Applications , 2018, IEEE Journal of Solid-State Circuits.