论文信息 - A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz

A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10-700 MHz

A PLL is fabricated in a 0.13 /spl mu/m logic process where leakage currents are high. The loop capacitor is implemented by a structure of poly and 9 metal layers. The VCO is implemented with common-mode feedback to compensate for leakage currents. Maximum VCO frequency is 1400 MHz. Typical power is 7 mW at 200 MHz. RMS jitter is 25.4 ps at 360 MHz.

R. Holzer

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