SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits

This paper proposes an innovative method for SPFD-based rewiring in Look-Up-Table-based (LUT-based) FPGA circuits. The new method adds new input wires to two or more LUT's in order to remove or to replace a target wire. There have been a few rewiring methods for FPGA circuits so far, such as the original SPFD-based optimization sometimes called Local Rewiring (LR), SPFD-based Global Rewiring (GR) and SPFD-based Enhanced Rewiring (ER). However, all of them replace one wire with other new input wire to one LUT but not with those to two or more LUT's. Moreover, the LR removes or replaces input wires with new one to the same LUT only, and the GR and ER topologically limit the LUT's where new input wires are added. Our new method, called One-to-Many Rewiring (OMR), loosens such topological constraints for more flexible FPGA circuit transformation so that it is easier to import constraints on physical design to the logic optimization. The experimental results show our OMR can transform FPGA circuits more flexibly than the LR, GR and ER, by introducing the new manipulation, wire addition. The OMR can rewire 1.2 times as many wires as the existing methods, especially, the ER. The computation time is as short as the existing methods.

[1]  Hiroshi Sawada,et al.  A General Framework to Use Various Decomposition Methods for LUT Network Synthesis , 2001 .

[2]  Masaki Nakanishi,et al.  Robust Quantum Algorithms with $\eps$-Biased Oracles , 2006 .

[3]  Masaki Nakanishi,et al.  TOWARD A PRACTICAL ENVIRONMENT FOR QUANTUM PROGRAMMING , 2005 .

[4]  Masaki Nakanishi,et al.  Cheater Identifiable Quantum Secret Sharing Schemes , 2005 .

[5]  平野 照比古 区間数による多項式の評価について (Computer Algebra : Algorithms, Implementations and Applications) , 2002 .

[6]  Shih-Chieh Chang,et al.  Perturb and simplify: multilevel Boolean network optimizer , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Hiroshi Sawada,et al.  Restricted simple disjunctive decompositions based on grouping symmetric variables , 1997, Proceedings Great Lakes Symposium on VLSI.

[8]  S. Yamashita,et al.  An Efficient Method for Generating Kernels on Implicit Cube Set Representations , 1999 .

[9]  Malgorzata Marek-Sadowska,et al.  Post-layout Logic Restructuring For Performance Optimization , 1997, Proceedings of the 34th Design Automation Conference.

[10]  Masahiro Kitagawa,et al.  Explicit implementation of quantum circuits on a quantum-cellular-automata-like architecture , 2005 .

[11]  Yahiko Kambayashi,et al.  Optimization methods for lookup-table-based FPGAs using transduction method , 1995, ASP-DAC '95.

[12]  Shih-Chieh Chang,et al.  Postlayout logic restructuring using alternative wires , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Premachandran R. Menon,et al.  Multi-level Logic Optimization By Implication Analysis , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[14]  田中 克典,et al.  Transformation-Based Logic Design for RSFQ Logic Circuits (デザインガイア 2004--VLSI設計の新しい大地を考える研究会) , 2004 .

[15]  Hiroshi Sawada,et al.  An integrated approach for synthesizing LUT networks , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[16]  Yamashita Shigeru,et al.  Secure Processor Architecture for High-Speed Verification of Memory Integrity , 2006 .

[17]  Jason Cong,et al.  A new enhanced SPFD rewiring algorithm , 2002, ICCAD 2002.

[18]  Andris Ambainis,et al.  Quantum Identification of Boolean Oracles , 2004, STACS.

[19]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[20]  Yahiko Kambayashi,et al.  Transformation rules for designing CNOT-based quantum circuits , 2002, DAC '02.

[21]  Yucheng Wang,et al.  LIBRA—a library-independent framework for post-layout performance optimization , 1998, ISPD '98.

[22]  Andris Ambainis,et al.  Robust Quantum Algorithms for Oracle Identification (計算機科学基礎理論とその応用 研究集会報告集) , 2004 .

[23]  Andris Ambainis,et al.  Improved algorithms for quantum identification of Boolean oracles , 2006, Theor. Comput. Sci..

[24]  M. Nakanishi,et al.  A New Approach to Online FPGA Placement , 2006, 2006 40th Annual Conference on Information Sciences and Systems.

[25]  Shigeru Yamashita,et al.  Efficient Kernel Generation Based on Implicit Cube Set Representations and Its Applications , 2000 .

[26]  Kazuo Iwama,et al.  A complete set of transformation rules for quantum Boolean circuits with CNOT gates , 2002 .

[27]  D. Michael Miller,et al.  Decision Diagram Data Structure to Represent Quantum Circuit , 2006 .

[28]  Kazuo Iwama,et al.  Quantum Sampling for Balanced Allocations , 2003, IEICE Trans. Inf. Syst..

[29]  Kazuyoshi Takagi,et al.  A transduction-based framework to synthesize RSFQ circuits , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[30]  Yamashita Shigeru,et al.  Online FPGA Placement under I/O Timing Constraints , 2005 .

[31]  Hiroshi Sawada,et al.  Restructuring logic representations with easily detectable simple disjunctive decompositions , 1998, Proceedings Design, Automation and Test in Europe.

[32]  Masaki Nakanishi,et al.  An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs , 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[33]  Hiroshi Sawada,et al.  CAD transactions best paper a ward "SPFD: a new method to express functional flexibility" , 2002, IEEE Circuits and Systems Magazine.

[34]  A. Nagoya,et al.  An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[35]  Masahito Hayashi,et al.  (4, 1)-Quantum Random Access Coding Does Not Exist , 2006, 2006 IEEE International Symposium on Information Theory.

[36]  Yahiko Kambayashi,et al.  The Transduction Method-Design of Logic Networks Based on Permissible Functions , 1989, IEEE Trans. Computers.

[38]  Raymond H. Putra,et al.  Quantum lower bounds for the Goldreich-Levin problem , 2006, Inf. Process. Lett..

[39]  Shih-Chieh Chang,et al.  Circuit Optimization by Rewiring , 1999, IEEE Trans. Computers.

[40]  Kwang-Ting Cheng,et al.  Combinational and sequential logic optimization by redundancy addition and removal , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[41]  Kazuo Iwama,et al.  General Bounds for Quantum Biased Oracles , 2005 .

[42]  Hiroshi Sawada,et al.  New methods to find optimal non-disjoint bi-decompositions , 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

[43]  Jason Cong,et al.  A new enhanced SPFD rewiring algorithm [logic IC layout] , 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

[44]  K. Watanabe,et al.  Event-oriented computing with reconfigurable platform , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[45]  Hiroshi Sawada,et al.  An Efficient Method for Finding an Optimal Bi-Decomposition (Special Section on VLSI Design and CAD Algorithms) , 1998 .

[46]  Shigeru Yamashita,et al.  Restructuring Logic Representations with Simple Disjunctive Decompositions (Special Section on VLSI Design and CAD Algorithms) , 1998 .

[47]  Jason Cong,et al.  SPFD-based global rewiring , 2002, FPGA '02.

[48]  S. Yang,et al.  Logic Synthesis and Optimization Benchmarks User Guide Version 3.0 , 1991 .

[49]  Kazuo Iwama,et al.  Quantum Biased Oracles , 2005 .

[50]  Rudy Raymond,et al.  (4,1)-Quantum random access coding does not exist—one qubit is not enough to recover one of four bits , 2006, quant-ph/0604061.

[51]  Yahiko Kambayashi,et al.  SPFD-based one-to-many rewiring , 2004, FPGA '04.

[52]  Masaki Nakanishi,et al.  QUANTUM PUSHDOWN AUTOMATA THAT CAN DETERMINISTICALLY SOLVE A CERTAIN PROBLEM , 2005 .

[53]  Masaki Nakanishi,et al.  Reconfigurable 1-Bit Processor Array with Reduced Wirng Area , 2005, International Conference on Engineering of Reconfigurable Systems and Algorithms.

[54]  山下 茂,et al.  Transmitting classical information on the quantum network efficiently , 2005 .

[55]  Yahiko Kambayashi,et al.  SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits , 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[56]  Yahiko Kambayashi,et al.  Reduction of the Number of FPGA Blocks by Maximizing Flexibility of Internal Functions (Special Section on VLSI Design and CAD Algorithms) , 1998 .

[57]  Hiroshi Sawada,et al.  A new method to express functional permissibilities for LUT based FPGAs and its applications , 1996, Proceedings of International Conference on Computer Aided Design.