A 52GHz Millimeter-Wave PLL Synthesizer for 60GHz WPAN Radio

In this paper, we present the design of 52-GHz frequency synthesizer for 60 GHz WPAN application. The PLL consists of 26 GHz PLL and 52 GHz frequency doubler, generating two channels of output carriers with 2.08 GHz step by using high-speed four-modulus divider. The proposed PLL represents phase noise of - 89 dBc/Hz from 26.2 GHz carrier and - 81 dBc/Hz from 52.4 GHz carrier, at 1 MHz offset, respectively. Also, its integrated RMS phase noise from 1 MHz to 100 MHz is measured as 7.42deg Output frequency tuning range from the PLL is 50 to 53-GHz. The synthesizer including frequency doubler consumes 160 mA at 2.5V supply voltage and occupies 1.2 times 1.0 mm2 chip area.

[1]  B. Floyd,et al.  A silicon 60GHz receiver and transmitter chipset for broadband communications , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[2]  Toshiya Mitomo,et al.  A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[4]  Ryuichi Fujimoto,et al.  A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS , 2009, IEICE Trans. Electron..

[5]  B. Gaucher,et al.  A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications , 2006, IEEE Journal of Solid-State Circuits.

[6]  Shen-Iuan Liu,et al.  A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  B. Razavi,et al.  A 60-GHz CMOS receiver front-end , 2006, IEEE Journal of Solid-State Circuits.

[8]  F. Gruson,et al.  A frequency doubler with high conversion gain and good fundamental suppression , 2004, 2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535).

[9]  F. Herzel,et al.  A fully integrated BiCMOS PLL for 60 GHz wireless applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[10]  B.A. Floyd A 15 to 18-GHz Programmable Sub-Integer Frequency Synthesizer for a 60-GHz Transceiver , 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

[11]  Hyun-Kyu Yu,et al.  A 15-GHz 7-channel SiGe:C PLL for 60-GHz WPAN Application , 2007, 2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.

[12]  Yanping Ding,et al.  A 50-GHz Phase-Locked Loop in 130-nm CMOS , 2006, IEEE Custom Integrated Circuits Conference 2006.