On topological via minimization and routing

The authors consider the topological via minimization problem in a bounded region. The problem is known to be NP-complete. An approximation algorithm is proposed for this problem, which solves the two-layer topological via minimization problem in a bounded region with at most 0.25m* more vias than the optimal number of vias, where m* is the size of the maximum two-planar subset of nets for the given problem. A graph-theoretic heuristic algorithm is also proposed to obtain a geometric routing from a topological solution.<<ETX>>

[1]  Wentai Liu,et al.  Unconstrained via minimization for topological multilayer routing , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Donald S. Fussell,et al.  Topological channel routing [VLSI] , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  KENNETH J. SUPOWIT,et al.  Finding a Maximum Planar Subset of a Set of Nets in a Channel , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Ahsan Abdullah,et al.  Topological via minimization and routing , 1991, [1991] Proceedings. First Great Lakes Symposium on VLSI.

[5]  Malgorzata Marek-Sadowska.  An Unconstrained Topological Via Minimization Problem for Two-Layer Routing , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Jason Cong,et al.  On the k-layer planar subset and via minimization problems , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[7]  Chi-Ping Hsu.  Minimum-Via Topological Routing , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Toshinobu Kashiwabara,et al.  Exact algorithms for multilayer topological via minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Majid Sarrafzadeh,et al.  An optimal algorithm for the maximum two-chain problem , 1990, SODA '90.

[10]  Majid Sarrafzadeh,et al.  A new approach to topological via minimization , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..