Input pattern classification for transistor level testing of BiCMOS circuits

In BiCMOS, transistor stuck-OPEN faults exhibit delay faults in addition to sequential behavior. Stuck-ON faults cause enhanced I/sub DDQ/. The faulty behavior of Bipolar (TTL) and CMOS logic families is compared with BiCMOS. The faults in BiCMOS devices cause one or more parts (p-part or n-parts) of the circuit to exhibit a different state (conducting or nonconducting) from the fault-free circuit. An input pattern classification scheme is presented for different faults. These classes of patterns are then used to obtain test sets.<<ETX>>

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