An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter

We present an I/O-size second-order analog to digital converter (ADC) combined with a time-to-digital converter (TDC) and a voltage-to-time converter (VTC). Our proposed VTC is optimized for metal–oxide–metal (MOM) capacitances, and is charged to the MOM capacitances by an input voltage. In a standard 65-nm CMOS process, a signal to noise and distortion ratio (SNDR) of 50 dB (8 bits) is achievable at an input signal frequency of 78 kHz and a sampling rate of 20 MHz, where the respective area and power are 6468 mm2 and 509 μW. The measured maximum integral nonlinearity (INL) of the proposed ADC is −1.41 LSBs. The active area of the proposed ADC is smaller than an I/O buffer. The proposed ADC is useful as an ADC I/O. key words: ADC, I/O-size, VTC, MOM capacitance

[1]  Kenneth A. Townsend,et al.  A 2.5GS/s 3-bit time-based ADC in 90nm CMOS , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[2]  Chulwoo Kim,et al.  A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[3]  Tadahiro Kuroda,et al.  A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

[4]  Ehsan Afshari,et al.  A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS , 2011, IEEE Journal of Solid-State Circuits.

[5]  Shintaro Izumi,et al.  A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops , 2013, IEICE Trans. Electron..

[6]  Teresa H. Y. Meng,et al.  Adaptive Resolution ADC Array for an Implantable Neural Sensor , 2011, IEEE Transactions on Biomedical Circuits and Systems.

[7]  Robert H. M. van Veldhoven,et al.  A 1.2V 121-Mode CT ΔΣ Modulator for Wireless Receivers in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  A.A. Abidi,et al.  Phase Noise and Jitter in CMOS Ring Oscillators , 2006, IEEE Journal of Solid-State Circuits.

[9]  Peng Gao,et al.  A 2.8-to-8.5mW GSM/bluetooth/UMTS/DVB-H/WLAN fully reconfigurable CTΔΣ with 200kHz to 20MHz BW for 4G radios in 90nm digital CMOS , 2010, 2010 Symposium on VLSI Circuits.

[10]  Leonid Belostotski,et al.  A 5GS/s 4-bit time-based single-channel CMOS ADC for radio astronomy , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[11]  Franco Maloberti,et al.  A 84dB SNDR 100kHz bandwidth low-power single op-amp third-order ΔΣ modulator consuming 140μW , 2011, 2011 IEEE International Solid-State Circuits Conference.

[12]  Tadahiro Kuroda,et al.  A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS , 2012, IEEE Journal of Solid-State Circuits.

[13]  Chih-Cheng Hsieh,et al.  A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[14]  Ehsan Afshari,et al.  Delay-Line-Based Analog-to-Digital Converters , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

[15]  Ming-Dou Ker,et al.  A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals , 2004, IEEE Trans. Circuits Syst. II Express Briefs.

[16]  Gordon W. Roberts,et al.  Delta–Sigma A/D Conversion Via Time-Mode Signal Processing , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Shintaro Izumi,et al.  Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network , 2011, 2011 Proceedings of 20th International Conference on Computer Communications and Networks (ICCCN).

[18]  Chulwoo Kim,et al.  A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Shintaro Izumi,et al.  An 8-bit I/O-sized ADC with second-order TDC and MOM capacitor voltage-to-time converter , 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).