A wide-band DSO architecture based on three time interleaved channels

A DSO architecture consisting of three parallel channels, each of which includes a sampler and a cascaded synchronous ADC, is presented. Thanks to suitable time and frequency interleaving operations, the overall system bandwidth is three times that of each single ADC. The proposed architecture exploits in a better way the hardware resources with respect to classical time interleaving-based solutions, and grants lower noise floor with respect to pure frequency interleaving alternatives. It can approach the performance of the state of the art DSOs, namely 100 GHz analog bandwidth and 240 GSa/s sampling frequency, by exploiting three identical ADCs characterized by 33 GHz input bandwidth and 80 GSa/s sampling frequency.