I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration
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Naoto Horiguchi | Aaron Thean | Tom Schram | Marc Aoulaiche | Alessio Spessot | Anda Mocuta | Romain Ritzenthaler | Moonju Cho | Christian Caillat | Pierre C. Fazan | K. B. Noh | Y. Son
[1] A. Uedono,et al. Suppression of anomalous threshold voltage increase with area scaling for Mg- or La-incorporated high-k/Metal gate nMISFETs in deeply scaled region , 2010, 2010 Symposium on VLSI Technology.
[2] E. Simoen,et al. A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies , 2014, 2014 IEEE International Electron Devices Meeting.
[3] Muzaffer A. Siddiqi. Dynamic RAM: Technology Advancements , 2012 .
[4] Martin M. Frank. High-k / metal gate innovations enabling continued CMOS scaling , 2011 .
[5] Naoto Horiguchi,et al. A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond , 2014, IEEE Transactions on Electron Devices.