LMgr: A low-M emory global router with dynamic topology update and bending-aware optimum path search

Global routing remains a fundamental physical design problem. We observe that large circuits cause high memory cost1, and modern routers could not optimize the routing path of each two-pin subnet. In this paper, (1) we develop a dynamic topology update technique to improve routing quality (2) we improve the memory efficiency with negligible performance overhead (3) we prove the non-optimality of traditional maze routing algorithm (4) we develop a novel routing algorithm and prove that it is optimum (5) we design a new global router, LMgr, which integrates all the above techniques. The experimental results on the ISPD 2008 benchmark suite show that LMgr could outperform NTHU2.0, NTUgr, FastRoute3.0 and FGR1.1 on solution quality in 13 out of 16 benchmarks and peak memory cost in 15 out of 16 benchmarks, the average memory reduction over all the benchmarks is up to 77%.

[1]  Yih-Lang Li,et al.  NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Yue Xu,et al.  FastRoute3.0: A fast and high quality global router based on virtual capacity , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[3]  J.A. Roy,et al.  High-performance routing at the nanometer scale , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[4]  Dieter A. Mlynski,et al.  Automatic Variable-Width Routing for VLSI , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Michael D. Moffitt MaizeRouter: engineering an effective global router , 2008, ASP-DAC 2008.

[6]  Yue Xu,et al.  MGR: Multi-level global router , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[7]  Christoph Albrecht,et al.  Global routing by new approximation algorithms for multicommodityflow , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Chris C. N. Chu,et al.  FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Yao-Wen Chang,et al.  High-performance global routing with fast overflow reduction , 2009, 2009 Asia and South Pacific Design Automation Conference.

[10]  Gi-Joon Nam,et al.  The ISPD global routing benchmark suite , 2008, ISPD '08.

[11]  C. Y. Lee An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..

[12]  Majid Sarrafzadeh,et al.  Pattern routing: use and theory for increasing predictability andavoiding coupling , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Jin Hu,et al.  Completing high-quality global routes , 2010, ISPD '10.

[14]  Ta-Wei Wang,et al.  NTHU-Route 2.0: a fast and stable global router , 2008, ICCAD 2008.

[15]  Yih-Lang Li,et al.  Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing , 2009, 2009 Asia and South Pacific Design Automation Conference.

[16]  Azadeh Davoodi,et al.  Congestion analysis for global routing via integer programming , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[17]  Gi-Joon Nam,et al.  The ISPD2005 placement contest and benchmark suite , 2005, ISPD '05.