FPGA based implementation of FDCT using Distributed Arithmetic

The paper describes a new architecture for implementation of 8 × 8 FDCT (Fast Discrete Cosine Transform) using Distributed Arithmetic (DA). This proposed architecture combines both DA based approaches for distributed input vector and constant coefficients. The described Combined Distributed Arithmetic based DCT (CDA-DCT) architecture has been implemented on Virtex II FPGA, and shows fewer adders and saving exceeding 97% achieved.

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