A fully parallel learning neural network chip for real-time control

Presents a parallel learning neural network chip, which is used to perform real-time output feedback control on a nonlinear dynamic plant. The controlled plant is a simulated unstable combustion process. Neural networks provide an adaptive sub-optimal control that does not need any prior knowledge of the system. In addition, the hardware neural network presented here utilizes parallelism to achieve speed independent of the size of the network enabling real-time control. On-chip learning ability allows the hardware neural network to learn online as the plant is running and the plant parameters are changing. Also described is the experimental setup used to obtain the results.

[1]  Simon M. Tam,et al.  Implementation and performance of an analog nonvolatile neural network , 1993 .

[2]  John J. Paulos,et al.  A neural network learning algorithm tailored for VLSI implementation , 1994, IEEE Trans. Neural Networks.

[3]  Torsten Lehmann ECCOPUNCH: the Edinburgh classical conditioning pulsed neural chip , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[4]  Torsten Lehmann,et al.  On-chip learning in pulsed silicon neural networks , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[5]  Takashi Morie,et al.  An all-analog expandable neural network LSI with on-chip backpropagation learning , 1994, IEEE J. Solid State Circuits.

[6]  Katsunari Shibata,et al.  A self-learning digital neural network using wafer-scale LSI , 1993 .

[7]  H. C. Card,et al.  Analog CMOS deterministic Boltzmann circuits , 1993 .

[8]  Paul J. Werbos,et al.  Neurocontrol and elastic fuzzy logic: capabilities, concepts, and applications , 1993, IEEE Trans. Ind. Electron..

[9]  V D Kalanovic,et al.  Feedback error learning neural network for trans-femoral prosthesis. , 2000, IEEE transactions on rehabilitation engineering : a publication of the IEEE Engineering in Medicine and Biology Society.

[10]  A. Thakoor,et al.  Design of parallel hardware neural network systems from custom analog VLSI 'building block' chips , 1989, International 1989 Joint Conference on Neural Networks.

[11]  Soo-Young Lee,et al.  Subthreshold MOS implementation of neural networks with on-chip error backpropagation learning , 1993, Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan).

[12]  Ralph Etienne-Cummings,et al.  An analog neural computer with modular architecture for real-time dynamic computations , 1992 .

[13]  Toshiyuki Furuta,et al.  Neural network LSI chip with on-chip learning , 1991, IJCNN-91-Seattle International Joint Conference on Neural Networks.

[14]  R. Palmer,et al.  Introduction to the theory of neural computation , 1994, The advanced book program.

[15]  G. Goto,et al.  A 54*54-b regularly structured tree multiplier , 1992 .

[16]  Yuzo Hirai Recent VLSI neural networks in Japan , 1993, J. VLSI Signal Process..

[17]  H. Shinohara,et al.  A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses , 1992 .

[18]  Yuping He,et al.  A charge-based on-chip adaptation Kohonen neural network , 1993, IEEE Trans. Neural Networks.

[19]  S. Neusser,et al.  Parallel digital neural hardware for controller design , 1996 .

[20]  F. J. Kub,et al.  Programmable analog vector-matrix multipliers , 1990 .

[21]  J. J. Paulos,et al.  Artificial neural networks using MOS analog multipliers , 1990 .

[22]  L. Rayleigh,et al.  The theory of sound , 1894 .

[23]  Leonardo Reyneri Neuro-Fuzzy Hardware: Design, Development and Performance , 1998 .

[24]  José Luis Huertas,et al.  A CMOS analog adaptive BAM with on-chip learning and weight refreshing , 1993, IEEE Trans. Neural Networks.

[25]  T. G. Habetler,et al.  Identification and control of induction motor stator currents using fast on-line random training of a neural network , 1995, IAS '95. Conference Record of the 1995 IEEE Industry Applications Conference Thirtieth IAS Annual Meeting.

[26]  Tetsuro Itakura,et al.  Neuro chips with on-chip back-propagation and/or Hebbian learning , 1992 .

[27]  R. S. Gyurcsik,et al.  An analog VLSI neural network with on-chip perturbation learning , 1997, IEEE J. Solid State Circuits.

[28]  D. T. Harrje Liquid propellant rocket combustion instability , 1972 .

[29]  Ralf Der,et al.  Building Nonlinear Data Models with Self-Organizing Maps , 1996, ICANN.

[30]  A. Masaki,et al.  Neural networks in CMOS: a case study , 1990, IEEE Circuits and Devices Magazine.

[31]  Yannis Tsividis,et al.  A reconfigurable VLSI neural network , 1992 .

[32]  Kuldip S. Rattan,et al.  Real-time tracking control of a DC motor using a neural network , 1995, Proceedings of the IEEE 1995 National Aerospace and Electronics Conference. NAECON 1995.

[33]  Thomas Kailath,et al.  Linear Systems , 1980 .

[34]  Torsten Lehmann,et al.  Mixed analog/digital matrix-vector multiplier for neural network synapses , 1996 .

[35]  Marwan A. Jabri,et al.  Weight perturbation: an optimal architecture and learning technique for analog VLSI feedforward and recurrent multilayer networks , 1992, IEEE Trans. Neural Networks.

[36]  K. Hirotsu,et al.  An analog neural network chip with random weight change learning algorithm , 1993, Proceedings of 1993 International Conference on Neural Networks (IJCNN-93-Nagoya, Japan).

[37]  C. Schneider,et al.  Analog CMOS synaptic learning circuits adapted from invertebrate biology , 1991 .

[38]  Yedidia Neumeier,et al.  A procedure for real-time mode decomposition, observation, and prediction for active control of combustion instabilities , 1997, Proceedings of the 1997 IEEE International Conference on Control Applications.

[39]  Jin Liu,et al.  High speed on-line neural network control of an induction motor immune to analog circuit nonidealities , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[40]  Daniele D. Caviglia,et al.  An experimental analog VLSI neural network with on-chip back-propagation learning , 1992, ESSCIRC '92: Eighteenth European Solid-State Circuits conference.

[41]  S. Tam,et al.  An electrically trainable artificial neural network (ETANN) with 10240 'floating gate' synapses , 1990, International 1989 Joint Conference on Neural Networks.

[42]  Torsten Lehmann,et al.  An analog CMOS chip set for neural networks with arbitrary topologies , 1993, IEEE Trans. Neural Networks.

[43]  Claudio Turchetti,et al.  An Analog CMOS Neural Network with On-Chip Learning and Multilevel Weight Storage , 1996, ICANN.

[44]  Jerzy B. Lont Analog CMOS implementation of a multi-layer perceptron with nonlinear synapses , 1992, IEEE Trans. Neural Networks.