A novel buffer circuit for energy efficient signaling in dual-VDD systems

We propose a novel buffer circuit that allows on-chip signaling for dual-VDD systems at the lower supply (VDDL) with a higher performance and smaller area than the standard buffer. The proposed dual-VDD buffer uses a pull-up PMOS connected to the higher supply (VDDH) rail in parallel with a standard buffer connected to VDDL. The VDDH pull-up PMOS turns on only briefly during a rising transition to aid the VDDL pull-up PMOS but avoids contention at steady state. The higher current drive with the VDDH PMOS allows a favorable trade-off of a considerable reduction in the VDDL buffer size for a small increase in the VDDH PMOS size. This trade-off is especially useful for meeting aggressive delay targets with the lower supply and allows the dual-VDD buffer to increase performance (up to 22%) compared to the standard buffer at VDDL, while still consuming less energy than VDDH signaling. The dual-VDD buffer also achieves gains in energy (up to 17%), buffer area (up to 56%) and peak current (up to 33%) at delay targets that can be met with standard buffers using VDDL.

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