Parallel architectures for 8*8 discrete cosine transforms

The design of multiplier-free parallel architectures for computing the 8*8 discrete cosine transform (DCT) is addressed. The focus is on direct methods, which avoid a row-column decomposition. Two architectures are proposed and compared. One uses polynomial transforms; the other computes the DCT via the Walsh-Hadamard transform (WHT). Both architectures achieve a high degree of parallelism and regularity. The architectures are designed for HDTV sampling rates and can be efficiently realized in CMOS technology.<<ETX>>

[1]  N. Cho,et al.  Fast algorithm and implementation of 2-D discrete cosine transform , 1991 .

[2]  D. Birreck,et al.  Classification for 2D-DCTs and a new architecture with distributed arithmetic , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[3]  Ali Habibi,et al.  Direct Computation Of Higher-Order Dct Coefficients From Lower-Order Dct Coefficients , 1984, Optics & Photonics.

[4]  Martin Vetterli,et al.  Fast 2-D discrete cosine transform , 1985, ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[5]  H. Nussbaumer,et al.  Fast computation of discrete Fourier transforms using polynomial transforms , 1979 .

[6]  N. Ahmed,et al.  Discrete Cosine Transform , 1996 .