Formal Verification and Diagnosis of CombinationalCircuit Designs with Propositional Logic

Zero-defect is extremely important for VLSI designs. Formal techniques for verifying the correctness of logic designs overcome the limits of test case simulation. Many formal systems have been proposed for verification purpose. However, verification of VLSI designs is not enough. It would be equally or more important to correct wrong designs. Little attention has been paid on diagnosis of logic designs. We propose a formal system, based on a propositional logic theorem prover, to verify a combinational logic design and to fix the design if it is incorrect. By referring to the models obtained for an incorrect design and applying some heuristics, the system can locate errors and correct the design in an intelligent way.

[1]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Manfred Weyerer,et al.  Testability of electronic circuits , 1992 .

[3]  Alfred V. Aho,et al.  The Design and Analysis of Computer Algorithms , 1974 .

[4]  T. Larrabee.  Efficient generation of test patterns using Boolean satisfiability , 1990 .

[5]  Ralph W. Wilkerson,et al.  Automated circuit diagnosis using first order logic tools , 1988, IEA/AIE '88.

[6]  Anthony S. Wojcik,et al.  Formal Design Verification of Digital Systems , 1983, 20th Design Automation Conference Proceedings.

[7]  Hideo Fujiwara,et al.  The Complexity of Fault Detection Problems for Combinational Logic Circuits , 1982, IEEE Transactions on Computers.

[8]  Hilary Putnam,et al.  A Computing Procedure for Quantification Theory , 1960, JACM.

[9]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[10]  Randall Davis,et al.  Diagnostic Reasoning Based on Structure and Behavior , 1984, Artif. Intell..

[11]  Harry G. Barrow,et al.  VERIFY: A Program for Proving Correctness of Digital Hardware Designs , 1984, Artif. Intell..

[12]  Alexander Miczo,et al.  Digital logic testing and simulation , 1986 .

[13]  David A. Plaisted,et al.  A Structure-Preserving Clause Form Translation , 1986, J. Symb. Comput..

[14]  Wolfgang Bibel,et al.  Automated Theorem Proving , 1987, Artificial Intelligence / Künstliche Intelligenz.

[15]  Keith Hanna,et al.  Specification and Verification using Higher-Order Logic , 1985 .

[16]  Brian C. Williams,et al.  Diagnosing Multiple Faults , 1987, Artif. Intell..

[17]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[18]  Melvin A. Breuer,et al.  Diagnosis and Reliable Design of Digital Systems , 1977 .

[19]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[20]  Edward A. Feigenbaum,et al.  Switching and Finite Automata Theory: Computer Science Series , 1990 .

[21]  Raymond Reiter,et al.  A Theory of Diagnosis from First Principles , 1986, Artif. Intell..

[22]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[23]  Alberto L. Sangiovanni-Vincentelli,et al.  PROTEUS : A Logic Verification System for Combinational Circuits , 1986, ITC.

[24]  M. Gordon.  HOL: A Proof Generating System for Higher-Order Logic , 1988 .

[25]  Robert S. Boyer,et al.  Computational Logic , 1990, ESPRIT Basic Research Series.

[26]  M. Bennett.  Proving correctness of asynchronous circuits using temporal logic , 1986 .

[27]  Michael R. Genesereth,et al.  The Use of Design Descriptions in Automated Diagnosis , 1984, Artif. Intell..

[28]  F. Joel Ferguson.  Book Review: Logic Design Principles by Edward J. McCluskey: Prentice-Hall Publishers, Englewood Cliffs, New Jersey, 549 pp., $39.95 , 1988, CARN.

[29]  Edmund M. Clarke,et al.  Automatic verification of asynchronous circuits using temporal logic , 1986 .

[30]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .

[31]  Mandalagiri S. Chandrasekhar,et al.  Application of Term Rewriting Techniques to Hardware Design Verification , 1987, 24th ACM/IEEE Design Automation Conference.

[32]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[33]  Dhiraj K. Pradhan,et al.  Fault-tolerant computing : theory and techniques , 1986 .