LMS-FIR based digital background calibration for the four-channel time-interleaved ADC
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[1] Ying-Hsi Lin,et al. An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[2] Yuriy Greshishchev,et al. A 24GS/s 6b ADC in 90nm CMOS , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[4] Fredrik Gustafsson,et al. Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.
[5] P. Hurst,et al. A digital background calibration technique for time-interleaved analog-to-digital converters , 1998, IEEE J. Solid State Circuits.
[6] Tai-Cheng Lee,et al. A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.
[7] Stephen H. Lewis,et al. Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter" , 2005, IEEE Trans. Circuits Syst. I Regul. Pap..
[8] W. Black,et al. Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.