A diagonal address generator for a Josephson memory circuit

The authors propose that a diagonal D address generator, which is useful for a single flux quantum (SFQ) memory cell in the triple coincidence scheme, can be performed by a full adder circuit. For the purpose of evaluating the D address generator for a 16-Kbit memory circuit, a 6-bit full adder circuit, using a current-steering flip-flop circuit, has been designed and fabricated with the lead-alloy process. Operating times for the address latch, carry generator, and sum generator were 150 ps, 250 ps/stage, and 1.4 ns, respectively. From these results, it has been estimated that the time necessary for the diagonal signal generation is 2.8 ns.

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