Evaluation of a Multithreaded Architecture for Defense Applications.

Abstract : Multithreading has received considerable attention in recent years as a promising way to hide memory latency in high performance computers, while providing access to a large and uniform shared memory. Tera Computer of Seattle has designed and built a state of the art multithreaded computer called the MTA. Its intended benefits are high processor utilization, scalable performance on applications that are difficult to parallelize, and reduced programming effort. The largest MTA and the only one outside of Seattle is at the San Diego Supercomputer Center (SDSC) on the campus of the University of California, San Diego (UCSD). Currently the MTA at SDSC has 8 processors. The performance and usability of the MTA for 14 defense relevant applications were evaluated in a two year project described here. The applications included seven standard kernels, five mini-applications, and two large applications. The evaluation was led by researchers at UCSD with collaborators at Caltech, Tera, Boeing, and Sanders/Lockheed Martin. UCSD researchers also carried out multithreaded scheduler and compiler studies. The principal findings of the project follow in the enclosed final report.

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