Design of Low-Power Multiplierless Linear-Phase FIR Filters
暂无分享,去创建一个
[1] Yong Lian,et al. A polynomial-time algorithm for designing FIR filters with power-of-two coefficients , 2002, IEEE Trans. Signal Process..
[2] Yong Ching Lim,et al. Optimization of Linear Phase FIR Filters in Dynamically Expanding Subexpression Space , 2010, Circuits Syst. Signal Process..
[3] Ya Jun Yu,et al. Single-Stage and Cascade Design of High Order Multiplierless linear phase FIR Filters Using Genetic Algorithm , 2019 .
[4] Linda S. DeBrunner,et al. Design of multiplierless FIR filters with an adder depth versus filter order trade-off , 2009, 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers.
[5] Arda Yurdakul,et al. An Algorithm for the Design of Low-Power Hardware-Efficient FIR Filters , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.
[6] Andrew G. Dempster,et al. Designing multiplier blocks with low logic depth , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[7] Chao-Liang Chen,et al. A trellis search algorithm for the design of FIR filters with signed-powers-of-two coefficients , 1999 .
[8] In-Cheol Park,et al. FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Mathias Faust,et al. Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[10] Qiang Zhang,et al. A Novel Hybrid Monotonic Local Search Algorithm for FIR Filter Coefficients Optimization , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.
[11] Y. Lim,et al. FIR filter design over a discrete powers-of-two coefficient space , 1983 .
[12] Andrew G. Dempster,et al. Transition analysis on FPGA for multiplier-block based FIR filter structures , 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).
[13] Juan M. Meneses,et al. Logic Depth and Power Consumption: A Comparative Study Between Standard Cells and FPGAs , 1998 .
[14] Ya Jun Yu,et al. Switching activity analysis and power estimation for multiple constant multiplier block of FIR filters , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).
[15] Yong Ching Lim,et al. Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[16] Lars Wanhammar,et al. Power Estimation for Ripple-Carry Adders with Correlated Input Data , 2004, PATMOS.
[17] Tapio Saramäki,et al. A systematic algorithm for the design of multiplierless FIR filters , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[18] Levent Aksoy,et al. Design of low-power multiple constant multiplications using low-complexity minimum depth operations , 2011, GLSVLSI '11.
[19] Kenny Johansson,et al. Estimation of the switching activity in shift-and-add based computations , 2009, 2009 IEEE International Symposium on Circuits and Systems.
[20] Lars Wanhammar,et al. ILP modelling of the common subexpression sharing problem , 2002, 9th International Conference on Electronics, Circuits and Systems.
[21] Ya Jun Yu,et al. Bit-Level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[22] Andrew G. Dempster,et al. Power analysis of multiplier blocks , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[23] Dong Shi,et al. Design of Linear Phase FIR Filters With High Probability of Achieving Minimum Number of Adders , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.