Using design based binning to improve defect excursion control for 45nm production
暂无分享,去创建一个
[1] I. Peterson,et al. Process-window sensitive full-chip inspection for design-tosilicon optimization in the sub-wavelength era , 2005, IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing 2005..
[2] Kevin M. Monahan,et al. Design and process limited yield at the 65-nm node and beyond , 2005, SPIE Advanced Lithography.
[3] J. H. Yeh,et al. Novel technique to separate systematic and random defects during 65nm and 45nm process development , 2007, SPIE Advanced Lithography.
[4] Scott Halle,et al. Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era , 2005, SPIE Advanced Lithography.