Synthesizable reconfigurable array targeting distributed arithmetic for system-on-chip applications

Summary form only given. Domain-specific reconfigurable arrays are embedded arrays optimized for one domain of applications providing performance improvements over generic embedded field programmable gate arrays (FPGAs). An embedded reconfigurable array that targets distributed arithmetic (DA) implementations is presented. DA includes calculations that are commonly found in multimedia applications, such as filtering and discrete cosine transform (DCT). Two benchmark DCT circuits are implemented on the array, on conventional FPGAs and on hardwired cores. The performance measured shows considerable improvements in area, power consumption and timing when comparing the presented array with FPGAs. Experimental results are provided which demonstrate the suitability of our architecture in low-power system-on-chip platforms targeting portable mobile devices.

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