论文信息 - A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning

A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning

Multiplying delay-locked loops (MDLLs) [1–5] have been shown to have improved jitter accumulation and tracking over VCO-based PLLs. By injecting the reference clock edge into the VCO at each reference cycle, an MDLL removes the accumulated jitter of the VCO. The principal challenge in MDLL design is to align the injected reference edge with the loop feedback signal. Timing mismatch between the reference edge and the VCO feedback edge, or offsets in the charge pump, would introduce a phase error in the injected edge. The error manifests as a period jitter or reference spur in the frequency domain. This effect limits the minimum jitter attained by the MDLL.

Ron Ho | Chih-Kong Ken Yang | Robert J. Drost | Amr Amin Hafez | Tamer A. Ali

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