An analog implementation of biologically plausible neurons using CCII building blocks

This study presents an analog implementation of the spiking neurons based on a piecewise-linear model. This model is a variation of the Izhikevich model, which is capable of reproducing different dynamic behaviors. The proposed circuit utilizes second generation current conveyors (CCII) building blocks. With the same topology and circuit values, this circuit can produce a wide variety of neuron behaviors just by tuning the reference current and voltage sources. In addition, since CCII can be considered as a building block for programmable analog arrays, based on the proposed circuit different neuron types can be implemented on programmable analog platforms. Simulation results are presented for different neuron behaviors with CMOS 350 nm ±1.5 V technology using HSPICE.

[1]  H. A. Alzaher,et al.  A CMOS fully balanced second-generation current conveyor , 2003 .

[2]  Jean-Pierre Chante,et al.  A Current Conveyor based Field Programmable Analog Array , 1996 .

[3]  Ralph Etienne-Cummings,et al.  A switched capacitor implementation of the generalized linear integrate-and-fire neuron , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[4]  Steve B. Furber,et al.  Modeling Spiking Neural Networks on SpiNNaker , 2010, Computing in Science & Engineering.

[5]  Mark Zwolinski,et al.  A modified Izhikevich model for circuit implementation of spiking neural networks , 2010, 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS).

[6]  Piotr Dudek,et al.  Compact silicon neuron circuit with spiking and bursting behaviour , 2008, Neural Networks.

[7]  K. Smith,et al.  A second-generation current conveyor and its applications , 1970, IEEE Transactions on Circuit Theory.

[8]  A. Hodgkin,et al.  A quantitative description of membrane current and its application to conduction and excitation in nerve , 1952, The Journal of physiology.

[9]  P.G. Gulak,et al.  CMOS implementation of a current conveyor-based field-programmable analog array , 1997, Conference Record of the Thirty-First Asilomar Conference on Signals, Systems and Computers (Cat. No.97CB36136).

[10]  Hassan Elwan,et al.  A novel CMOS current conveyor realization with an electronically tunable current mode filter suitable for VLSI , 1996 .

[11]  Jiann-Jong Chen,et al.  New building block: multiplication-mode current conveyor , 2009, IET Circuits Devices Syst..

[12]  Wouter A. Serdijn,et al.  A new CMOS current conveyors based translinear loop for log-domain circuit design , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[13]  Stephen P. DeWeerth,et al.  Adaptation in a VLSI model of a neuron , 1999 .

[14]  Nicolas Brunel,et al.  Lapicque’s 1907 paper: from frogs to integrate-and-fire , 2007, Biological Cybernetics.

[15]  Eugene M. Izhikevich,et al.  Simple model of spiking neurons , 2003, IEEE Trans. Neural Networks.

[16]  Yannick Bornat,et al.  Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[17]  Wulfram Gerstner,et al.  SPIKING NEURON MODELS Single Neurons , Populations , Plasticity , 2002 .