Crosstalk Noise Modeling analysis for RC Interconnect in Deep Sub-Micron VLSI Circuit

This thesis presents an approach to solve the VLSI (very large scale integration) layer assignment problems that will lead to the minimization of crosstalk noise. Using 2π model a closed form crosstalk noise modeling for on-chip VLSI RC interconnects is presented in this thesis. The interconnection can be modeled as distributed RC segments with sufficient accuracy for the low frequency of operation. When step input and saturated ramp input is applied to the aggressor which is adjacent to the victim net then this crosstalk noise modeling is perpetrated. In this thesis, the working model represents the noise voltage waveform. This thesis is worked to find out noise pulse width and noise amplitude for RC interconnection. In this thesis, the original 2π model is further simplified and it has simply closed form expressions, which is capable of measuring noise pulse width and noise amplitude for RC interconnect. The closed form expressions of a 2π model are simulated using Matlab. This model considers various parameters, such as coupling location (near the driver and near receiver) and course distributed RC characteristics for victim net.

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