SWiTEST: a switch level test generation system for CMOS combinational circuits

The authors present a switch level test generation system called SWiTEST. SWiTEST deals with bridging, breaking, stuck-open/on and stuck-at-faults. It employs both logic and current monitoring and takes into account the invalidation problem associated with stuck-open tests. The framework for SWiTEST is based on the PODEM algorithm. Some experimental results are presented and discussed. The experimental results imply that switch level test generation can be done in CPU time that is within an order of magnitude of that required for gate level test generation.<<ETX>>

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