The design of low-power CIFF structure second-order sigma-delta modulator

This paper presents the design and implementation of a low power sigma-delta modulator (SDM) with a standard 0.18-µm CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational trans-conductance amplifier(OTA). Using a chain of Integrators with weighted feed-forward summation (CIFF) structure and optimized single-stage class-A OTA with positive feedback to minimize the power consumption, the second-order SDM achieves a SNR of 64dB that be able to process the signal form DC to 16 KHz. The power consumption is only 18.1 uW from a 1-V supply.

[1]  D. Joseph,et al.  Optimization of Delta-Sigma ADC for Column-Level Data Conversion in CMOS Image Sensors , 2007, 2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007.

[2]  Bruce A. Wooley,et al.  The Design of Low-Voltage, Low-Power Sigma-Delta Modulators , 1998 .

[3]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[4]  Yi-Gyeong Kim,et al.  A 0.9-V 60-$\mu{\hbox {W}}$ 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range , 2008, IEEE Journal of Solid-State Circuits.

[5]  G.C. Temes,et al.  A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators , 2005, IEEE Journal of Solid-State Circuits.

[6]  Mohamad Sawan,et al.  A low-voltage 38/spl mu/W sigma-delta modulator dedicated to wireless signal recording applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[7]  Hoi-Jun Yoo,et al.  An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip , 2006 .

[8]  Shuenn-Yuh Lee,et al.  A Low-Voltage and Low-Power Adaptive Switched-Current Sigma–Delta ADC for Bio-Acquisition Microsystems , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  T. Tille,et al.  A 0.7-V MOSFET-only switched-opamp /spl Sigma//spl Delta/ modulator in standard digital CMOS technology , 2002 .

[10]  Hoi-Jun Yoo,et al.  An energy-efficient analog front-end circuit for a sub-1V digital hearing aid chip , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

[11]  Roubik Gregorian,et al.  Introduction to CMOS OP-AMPs and Comparators , 1999 .

[12]  G. Temes,et al.  Wideband low-distortion delta-sigma ADC topology , 2001 .