This paper describes an explicit, continuous and threshold voltage (Vth) based compact model of Independent Double Gate (IDG) MOSFET with undoped channel. This model is derived thanks to Poisson equation resolution. Without any fitting parameter or charge sheet approximation, it provides explicit analytical expressions of drain current considering long and short undoped transistor. Consequently, this is a fully analytical and predictive model allowing the description of planar DG MOSFET (symmetrical, asymmetrical and independent) as well as FinFET structures. The validity of this model is demonstrated by comparison with Atlas simulations. The model was implemented in VerilogA in order to test it and to design circuits. Simulation circuit results of a signal mixer and of an inverter are presented. Introduction: DG MOSFETs are promising devices because they can be scaled to the shortest channel length, particularly IDG MOSFETs because the front and the back gate can be independently driven. They enlarge the circuit design space. That is why a compact model is crucial to take advantage of this new technology. However, explicit IDG MOSFET compact model does not really exist. Indeed, existing models require numerical resolutions or are not valid in all operating modes: [1]-[4]. This article presents a Vth-based model of IDG MOSFET, which could be integrated in standard BSIM model. Then, the model was validated by confrontation with numerical simulations [5] and implemented in VerilogA to design circuits. Circuit simulation results are presented to illustrate its robustness. Vth model: We propose to model an IDG MOSFET, with undoped silicon film. IDG MOSFET is shown on Figure 1. L is the gate length, Tsi is the silicon film (or body) thickness, Tox1 and Tox2 are the front and the back gate oxide thicknesses, respectively. Vg1 and Vg2 are the front and the back gate voltages. Without generality loss, ∆Φm1 (respectively ∆Φm2), the work function difference between the front (respectively back) gate and the intrinsic silicon is supposed zero. To model this device, some assumptions were taken into account: Boltzmann statistics was chosen, the current is the sum of the diffusion and drift currents as in the Pao and Sah model, no quantum effect and no ballistic transport are considered. 1D Poisson equation is solved to derive the drain current Ids. Boundary conditions, electrical neutrality and physical assumptions allow getting explicit Ids. Poisson's equation within the gradual channel approximation is: ( ) ( ) ( ) − = t imref Si i u x y x n q dy y x d φ ψ e ψ , exp . . , 2 2 (1) Ψ(x,y) is the potential in the silicon film, q is the electron charge, ni the intrinsic doping, esi the silicon permittivity. ut is the thermal voltage and Φimref is the quasi Fermi level of electrons in the channel. Boundary conditions are: y Q Q T V s Si g ox g ox s m g ∂ ∂ − = + = ∆ − 1 1 1 1 1 1 1 1 ψ e e ψ φ (2) y Q Q T V s Si g ox g ox s m g ∂ ∂ = + = ∆ − 2 2 2 2 1 2 2 2 ψ e e ψ φ (3) Ψs1 and Ψs2 are the front and the back surface potentials. Qg1 and Qg2 are the front and the back gate charge. eox1 is the front gate oxide permittivity and eox2 is the back one. Electrical neutrality is expressed as: 0 2 1 = + + inv g g Q Q Q (4) Qinv is the inversion charge. 796 NSTI-Nanotech 2006, www.nsti.org, ISBN 0-9767985-8-1 Vol. 3, 2006 After integration of Poisson's equation between both interfaces with Gauss's law, we get: