An efficient global search algorithm for test generation

An efficient algorithm for test generation is presented. In the authors' algorithm, the test generation problem is formulated as the model of a global search of the sensitizing paths between the primary input and output nodes. Such a simple model offers significant efficiency improvements for test generation of large combinational circuits. The algorithms is tested using the ISCAS'85 benchmark combinational circuits. The experimental results on large circuits indicate that the algorithm outperforms deterministic test generation algorithms. The overall test system efficiently generates test vectors for large size combinational circuits with a high degree of test coverage.<<ETX>>

[1]  Srinivas Patil,et al.  Performance trade-offs in a parallel test generation/fault simulation environment , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[3]  Oscar H. Ibarra,et al.  Polynomially Complete Fault Detection Problems , 1975, IEEE Transactions on Computers.

[4]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..