SMART: A Simulator of Massive Architectures and Topologies

Many important results in the area of computer architecture have been achieved using simulat-ors. In this paper we present SMART, a simula-tor of parallel architectures. SMART provides a exible and eecient simulation environment that includes the most common interconnection networks and routing algorithms and gives the user basic mechanisms to deene the internal structure of the processing nodes. To show the characteristics of SMART, we analyze the relations between the degree of overlapping of the transpose FFT algorithm and the presence of a communication processor on a fat tree and on a bi-dimensional cube that have the same normalized communication bandwidth.

[1]  Fabrizio Petrini,et al.  Minimal vs. non Minimal Adaptive Routing on k-ary n-cubes , 1996, PDPTA.

[2]  Sandhya Dwarkadas,et al.  Efficient Simulation of Parallel Computer Systems , 1991, Int. J. Comput. Simul..

[3]  Erik Hagersten,et al.  The Cache Coherence Protocol of the Data Diffusion Machine , 1989 .

[4]  Luis Gravano,et al.  Storage-Efficient, Deadlock-Free Packet Routing Algorithms for Torus Networks , 1994, IEEE Trans. Computers.

[5]  Fabrizio Petrini,et al.  k-ary n-trees: high performance networks for massively parallel architectures , 1997, Proceedings 11th International Parallel Processing Symposium.

[6]  Kai Hwang,et al.  Advanced computer architecture - parallelism, scalability, programmability , 1992 .

[7]  José Duato.  A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks , 1995, IEEE Trans. Parallel Distributed Syst..

[8]  F. Leighton,et al.  Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes , 1991 .

[9]  Eric A. Brewer,et al.  PROTEUS: a high-performance parallel-architecture simulator , 1992, SIGMETRICS '92/PERFORMANCE '92.

[10]  Helen Davis,et al.  Tango introduction and tutorial , 1990 .

[11]  William J. Dally,et al.  The message-driven processor , 1992 .

[12]  Stephen R. Goldschmidt,et al.  Simulation of multiprocessors: accuracy and performance , 1993 .

[13]  Eric A. Brewer,et al.  Developing parallel applications using high-performance simulation , 1993, PADD '93.

[14]  David R. Keppel,et al.  Tools and Techniques for Building Fast Portable Threads Packages , 1993 .

[15]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[16]  Marvin Theimer,et al.  Tango Lite: a Multiprocessor Simulation Environment. Unpublished Intro- Duction and User's Guide, Figure 4: Low Communication/computation Ratio for 16 Virtual Processors Figure 3: Medium Communication/computation Ratio for 16 Virtual Processors Figure 2: High Communication/computation Ratio Using 16 , 2008 .

[17]  Frank Thomson Leighton.  Introduction to parallel algorithms and architectures: arrays , 1992 .

[18]  Fabrizio Petrini,et al.  Performance analysis of minimal adaptive wormhole routing with time-dependent deadlock recovery , 1997, Proceedings 11th International Parallel Processing Symposium.

[19]  Luigi M. Ricciardi,et al.  A Trace-Driven Simulator for Performance Evaluation of Cache-Based Multiprocessor Systems , 1995, IEEE Trans. Parallel Distributed Syst..

[20]  Kevin Bolding,et al.  Chaotic routing: design and implementation of an adaptive multicomputer network router , 1993 .

[21]  Vipin Kumar,et al.  The Scalability of FFT on Parallel Computers , 1993, IEEE Trans. Parallel Distributed Syst..