MORC: A manycore-oriented compressed cache
暂无分享,去创建一个
[1] David A. Wood,et al. Adaptive cache compression for high-performance processors , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..
[2] Harish Patil,et al. Pinballs: portable and shareable user-level checkpoints for reproducible analysis and simulation , 2014 .
[3] Xi Chen,et al. C-Pack: A High-Performance Microprocessor Cache Compression Algorithm , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[4] David Wentzlaff,et al. Execution Drafting: Energy Efficiency through Computation Deduplication , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[5] Martin Burtscher,et al. FPC: A High-Speed Compressor for Double-Precision Floating-Point Data , 2009, IEEE Transactions on Computers.
[6] Michael E. Wazlowski,et al. IBM Memory Expansion Technology (MXT) , 2001, IBM J. Res. Dev..
[7] Jim Jeffers,et al. Chapter 10 – Linux on the Coprocessor , 2013 .
[8] Nam Sung Kim,et al. Lossless and lossy memory I/O link compression for improving performance of GPGPU workloads , 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).
[9] David Wentzlaff,et al. Energy characterization of a tiled architecture processor with on-chip networks , 2003, ISLPED '03.
[10] David A. Wood,et al. Frequent Pattern Compression: A Significance-Based Compression Scheme for L2 Caches , 2004 .
[11] David Wentzlaff,et al. Processor: A 64-Core SoC with Mesh Interconnect , 2010 .
[12] Peter Deutsch,et al. GZIP file format specification version 4.3 , 1996, RFC.
[13] William J. Dally,et al. Scaling the Power Wall: A Path to Exascale , 2014, SC14: International Conference for High Performance Computing, Networking, Storage and Analysis.
[14] Somayeh Sardashti,et al. Decoupled compressed cache: Exploiting spatial locality for energy-optimized compressed caching , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[15] D. Burger,et al. Memory Bandwidth Limitations of Future Microprocessors , 1996, 23rd Annual International Symposium on Computer Architecture (ISCA'96).
[16] Peter Deutsch,et al. DEFLATE Compressed Data Format Specification version 1.3 , 1996, RFC.
[17] Lieven Eeckhout,et al. Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).
[18] Soontae Kim,et al. Residue cache: A low-energy low-area L2 cache architecture via compression and partial hits , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[19] Mark Horowitz,et al. Cache performance of operating system and multiprogramming workloads , 1988, TOCS.
[20] Pradeep Dubey,et al. Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU , 2010, ISCA.
[21] Norman P. Jouppi,et al. CACTI 5.0 , 2007 .
[22] S. Borkar,et al. An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.
[23] Ken Mai,et al. The future of wires , 2001, Proc. IEEE.
[24] David Wentzlaff,et al. PriME: A parallel and distributed simulator for thousand-core chips , 2014, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).
[25] Somayeh Sardashti,et al. Skewed Compressed Caches , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[26] Onur Mutlu,et al. Base-delta-immediate compression: Practical data compression for on-chip caches , 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).
[27] Steven K. Reinhardt,et al. A unified compressed memory hierarchy , 2005, 11th International Symposium on High-Performance Computer Architecture.
[28] Henry Hoffmann,et al. On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.
[29] Per Stenström,et al. SC2: A statistical compression cache scheme , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).
[30] Anant Agarwal,et al. Column-associative caches: a technique for reducing the miss rate of direct-mapped caches , 1993, ISCA '93.
[31] Per Stenström,et al. A Case for a Value-Aware Cache , 2014, IEEE Computer Architecture Letters.
[32] Pradeep Dubey,et al. Larrabee: A Many-Core x86 Architecture for Visual Computing , 2009, IEEE Micro.
[33] Vincent C. Gaudet,et al. A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.
[34] S. Pothula,et al. C-Pack : A High-Performance Microprocessor Cache Compression Algorithm , 2011 .
[35] Steven K. Reinhardt,et al. A fully associative software-managed cache design , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[36] A. Jaleel. Memory Characterization of Workloads Using Instrumentation-Driven Simulation A Pin-based Memory Characterization of the SPEC CPU 2000 and SPEC CPU 2006 Benchmark Suites , 2022 .
[37] James Reinders,et al. Intel Xeon Phi Coprocessor High Performance Programming , 2013 .
[38] Per Stenström,et al. Memory-Link Compression Schemes: A Value Locality Perspective , 2008, IEEE Transactions on Computers.
[39] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[40] Carl Ramey,et al. TILE-Gx100 ManyCore processor: Acceleration interfaces and architecture , 2011, 2011 IEEE Hot Chips 23 Symposium (HCS).
[41] Pradeep Dubey,et al. Convergence of Recognition, Mining, and Synthesis Workloads and Its Implications , 2008, Proceedings of the IEEE.
[42] Mark Horowitz,et al. Energy-Efficient Floating-Point Unit Design , 2011, IEEE Transactions on Computers.