New Systolic Arrays for CáAB 2 , Inversion, and Division in GFÖ2 m Ü

m). The architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. It is highly regular, modular, and, thus, well-suited to VLSI implementation. As compared to a previous systolic power-sum circuit with bidirectional data flow and the same throughput performance, the proposed one has smaller latency, consumes less chip area, and can more easily incorporate fault-tolerant design. Based on the new power-sum circuit, we also propose a parallel-in parallel-out systolic array with the maximum throughput for computing inverses/divisions in GF(2 m ). The proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area, latency, and fault tolerance.

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