Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder

High Efficiency Video Coding (HEVC/H.265) is an emerging standard for video compression that provides almost double compression efficiency at the cost of major computational complexity increase as compared to current industry-standard Advanced Video Coding (AVC/H.264). This work proposes a collaborative hardware and software scheme for complexity reduction in an HEVC Intra encoding system, with run-time adaptivity. Our scheme leverages video content properties which drive the complexity management layer (software) to generate a highly probable coding configuration. The intra prediction size and direction are estimated for the prediction unit which provides reduced computational-complexity. At the hardware layer, specialized coprocessors with enhanced reusability are employed as accelerators. Additionally, depending upon the video properties, the software layer administers the energy management of the hardware coprocessors. Experimental results show that a complexity reduction of up to 60 % and the energy reduction up to 42 % are achieved.

[1]  Debin Zhao,et al.  Gradient based fast mode decision algorithm for intra prediction in HEVC , 2012, 2012 2nd International Conference on Consumer Electronics, Communications and Networks (CECNet).

[2]  Sergio Bampi,et al.  Adaptive power management of on-chip video memory for Multiview Video Coding , 2012, DAC Design Automation Conference 2012.

[3]  Sergio Bampi,et al.  Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding , 2011, 2011 Design, Automation & Test in Europe.

[4]  Fernando Pereira,et al.  Fast rate distortion optimization for the emerging HEVC standard , 2012, 2012 Picture Coding Symposium.

[5]  Ilker Hamzaoglu,et al.  A high performance and low energy intra prediction hardware for High Efficiency Video Coding , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

[6]  Guangming Shi,et al.  An efficient VLSI architecture for 4×4 intra prediction in the High Efficiency Video Coding (HEVC) standard , 2011, 2011 18th IEEE International Conference on Image Processing.

[7]  Nuno Roma,et al.  Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems , 2010, 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP).

[8]  Muhammad Shafique,et al.  An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[9]  Peter Lambert,et al.  Improved intra mode signaling for HEVC , 2011, 2011 IEEE International Conference on Multimedia and Expo.

[10]  Muhammad Shafique,et al.  Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms , 2010, J. Signal Process. Syst..

[11]  Detlev Marpe,et al.  Performance analysis of HEVC-based intra coding for still image compression , 2012, 2012 Picture Coding Symposium.

[12]  Gary J. Sullivan,et al.  Overview of the High Efficiency Video Coding (HEVC) Standard , 2012, IEEE Transactions on Circuits and Systems for Video Technology.