Time-constrained scheduling of large pipelined datapaths

This paper addresses the most crucial optimization problem of high-level synthesis: scheduling. A formal framework is described that was tailored specifically for the definition and investigation of the time-constrained scheduling problem of pipelined datapaths. Theoretical results are presented on the complexity of the problem. Moreover, two new heuristic algorithms are introduced. The first one is a genetic algorithm, which, unlike previous approaches, searches the space of schedulings directly. The second algorithm realizes a heuristic search using constraint logic programming methods. The performance of the proposed algorithms has been evaluated on a set of benchmarks and compared to previous approaches.

[1]  Niraj K. Jha,et al.  Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[2]  Péter Arató,et al.  High Level Synthesis of Pipelined Datapaths , 2001 .

[3]  Jochen A. G. Jess,et al.  Exact scheduling strategies based on bipartite graph matching , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[4]  Imtiaz Ahmad,et al.  TLS: A Tabu Search Based Scheduling Algorithm for Behavioral Synthesis of Functional Pipelines , 2000, Comput. J..

[5]  M. Golumbic Algorithmic Graph Theory and Perfect Graphs (Annals of Discrete Mathematics, Vol 57) , 2004 .

[6]  Zoltán Ádám Mann,et al.  Algorithmic aspects of hardware/software partitioning , 2005, TODE.

[7]  Majid Sarrafzadeh,et al.  A super-scheduler for embedded reconfigurable systems , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[8]  Taewhan Kim,et al.  An integrated algorithm for memory allocation and assignment in high-level synthesis , 2002, DAC '02.

[9]  Giovanni De Micheli,et al.  Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Fei Sha Register-constrained Loop Scheduling for Optimizing Time and Memory Operations , 1998 .

[11]  Miodrag Potkonjak,et al.  Behavioral optimization using the manipulation of timing constraints , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Margarida F. Jacome,et al.  CALiBeR: a software pipelining algorithm for clustered embedded VLIW processors , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[13]  Sabih H. Gerez,et al.  Generation, Genetic Optimization and VHDL-Based Verification of Detailed Iterative Static Schedules for Multiprocessor Systems , 1999 .

[14]  M. Golumbic Algorithmic graph theory and perfect graphs , 1980 .

[15]  Krzysztof Kuchcinski,et al.  An approach to high-level synthesis using constraint logic programming , 1998, Proceedings. 24th EUROMICRO Conference (Cat. No.98EX204).

[16]  J.A.G. Jess,et al.  High-level synthesis scheduling and allocation using genetic algorithms based on constructive topological scheduling techniques , 1995, Proceedings of 1995 IEEE International Conference on Evolutionary Computation.

[18]  Lawrence. Davis,et al.  Handbook Of Genetic Algorithms , 1990 .

[19]  Edwin H.-M. Sha,et al.  Loop scheduling algorithm for timing and memory operation minimization with register constraint , 1998, 1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374).

[20]  Zoltán Ádám Mann,et al.  TIME-CONSTRAINED DESIGN OF PIPELINED CONTROL-INTENSIVE SYSTEMS , 2005 .

[21]  Sabih H. Gerez,et al.  List Scheduling for Iterative Data-Flow Graphs , 1995 .

[22]  Román Hermida,et al.  High-level synthesis of multiple-precision circuits independent of data-objects length , 2002, DAC '02.

[23]  Alexander Schrijver,et al.  Theory of linear and integer programming , 1986, Wiley-Interscience series in discrete mathematics and optimization.

[24]  R. Möhring Algorithmic graph theory and perfect graphs , 1986 .

[25]  Edwin H.-M. Sha,et al.  Imprecise task schedule optimization , 1997, Proceedings of 6th International Fuzzy Systems Conference.

[26]  Niraj K. Jha,et al.  : a novel scheduling technique for control-flow intensive behavioral descriptions , 1997, ICCAD 1997.

[27]  Werner Kinnebrock,et al.  OPTIMIERUNG MIT GENETISCHEN UND SELEKTIVEN ALGORITHMEN , 1994 .

[28]  Majid Sarrafzadeh,et al.  Algorithmic aspects of uncertainty driven scheduling , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[29]  Xuejia Lai,et al.  Markov Ciphers and Differential Cryptanalysis , 1991, EUROCRYPT.

[30]  Béla Bollobás,et al.  The chromatic number of random graphs , 1988, Comb..

[31]  J. Tukey,et al.  An algorithm for the machine calculation of complex Fourier series , 1965 .

[33]  Forrest Brewer,et al.  Representing and scheduling looping behavior symbolically , 2000, Proceedings 2000 International Conference on Computer Design.

[34]  Giovanni De Micheli,et al.  Constrained resource sharing and conflict resolution in Hebe , 1991, Integr..

[35]  Gary L. Miller,et al.  The Complexity of Coloring Circular Arcs and Chords , 1980, SIAM J. Algebraic Discret. Methods.

[36]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[37]  P. Arato,et al.  Hardware-software partitioning in embedded system design , 2003, IEEE International Symposium on Intelligent Signal Processing, 2003.

[38]  Edwin Hsing-Mean Sha,et al.  Rotation Scheduling: A Loop Pipelining Algorithm , 1993, 30th ACM/IEEE Design Automation Conference.

[39]  Pierre G. Paulin,et al.  Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[40]  Z. Mann,et al.  Genetic Scheduling Algorithm for High-Level Synthesis , 2002 .

[41]  Sabih H. Gerez,et al.  A Genetic Approach to the Overlapped Scheduling of Iterative Data-Flow Graphs for Target Architectures with Communication Delays , 1997 .

[42]  Hiroaki Kunieda,et al.  An optimal scheduling method for parallel processing system of array architecture , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.