An evolution to crossbar switches with virtual output queuing and buffered cross points

Input queued (IQ) switch architectures with virtual output queues (VOQ) scale up to very high speeds and have been a subject of intense research in the past decade. VOQ IQ switches require switch matrix scheduling algorithms to match input ports to out ports. In this tutorial article, we present an overview of switch matrix scheduling for VOQ IQ switches with crossbar switch fabrics. We then describe what we believe will be the next generation of high-speed crossbar switches: the evolution of IQ switches to combined input and crossbar queued (CICQ) switches. With the continued increase in density of VLSI, sufficient buffering at crossbar cross points for one cell or packet has become feasible to implement. We show how CICQ switches have simple schedulers and result in lower delay than IQ switches. Both IQ and CICQ switches have unstable regions. We show how a threshold and bursting technique can feasibly achieve stability. We also show how CICQ switches are better suited (than IQ switches) for switching of variable-length packets such as IP packets. Many challenges remain in IQ and CICQ switches. In particular, the inclusion of QoS scheduling methods that are currently only suitable for output queued switches is a major open problem.

[1]  Erwin P. Rathgeb,et al.  Buffering concepts for ATM switching networks , 1988, IEEE Global Telecommunications Conference and Exhibition. Communications for the Information Age.

[2]  Thomas E. Anderson,et al.  High speed switch scheduling for local area networks , 1992, ASPLOS V.

[3]  Satish Rao,et al.  Scheduling algorithms for input-queued switches: randomized techniques and experimental evaluation , 2000, Proceedings IEEE INFOCOM 2000. Conference on Computer Communications. Nineteenth Annual Joint Conference of the IEEE Computer and Communications Societies (Cat. No.00CH37064).

[4]  Dimitrios N. Serpanos,et al.  Two-dimensional round-robin schedulers for packet switches with multiple input queues , 1994, TNET.

[5]  Romano Fantacci,et al.  Performance evaluation of input and output queueing techniques in ATM switching systems , 1993, IEEE Trans. Commun..

[6]  Dan Keun Sung,et al.  High-performance variable-length packet scheduling algorithm for IP traffic , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).

[7]  Khaled Ben Letaief,et al.  Efficient scheduling of variable-length IP packets on high-speed switches , 1999, Seamless Interconnection for Universal Services. Global Telecommunications Conference. GLOBECOM'99. (Cat. No.99CH37042).

[8]  Eiji Oki,et al.  CIXOB-k: combined input-crosspoint-output buffered packet switch , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).

[9]  Hui Zhang,et al.  Implementing distributed packet fair queueing in a scalable switch architecture , 1998, Proceedings. IEEE INFOCOM '98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No.98.

[10]  Vinita Singhal,et al.  High-Speed Buffered Crossbar Switch Design Using Virtex-EM Devices , 2000 .

[11]  Nick McKeown,et al.  A Quantitative Comparison of Iterative Scheduling Algorithms for Input-Queued Switches , 1998, Comput. Networks.

[12]  Sung-Mo Kang,et al.  Matrix unit cell scheduler (MUCS) for input-buffered ATM switches , 1998, IEEE Communications Letters.

[13]  Panayotis Antoniadis,et al.  FIRM: a class of distributed scheduling algorithms for high-speed ATM switches with multiple input queues , 2000, Proceedings IEEE INFOCOM 2000. Conference on Computer Communications. Nineteenth Annual Joint Conference of the IEEE Computer and Communications Societies (Cat. No.00CH37064).

[14]  Masayoshi Nabeshima.  Performance Evaluation of a Combined Input- and Crosspoint-Queued Switch , 2000 .

[15]  Nick McKeown,et al.  The iSLIP scheduling algorithm for input-queued switches , 1999, TNET.

[16]  J. Chao.  Saturn: a terabit packet switch using dual round robin , 2000 .

[17]  Ken Christensen,et al.  A parallel-polled virtual output queued switch with a buffered crossbar , 2001, 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552).

[18]  Nicolas D. Georganas,et al.  16*16 limited intermediate buffer switch module for ATM networks , 1991, IEEE Global Telecommunications Conference GLOBECOM '91: Countdown to the New Millennium. Conference Record.

[19]  Nick McKeown,et al.  Matching output queueing with a combined input/output-queued switch , 1999, IEEE J. Sel. Areas Commun..

[20]  Hui Zhang,et al.  Service disciplines for guaranteed performance service in packet-switching networks , 1995, Proc. IEEE.

[21]  Anujan Varma,et al.  Providing bandwidth guarantees in an input-buffered crossbar switch , 1995, Proceedings of INFOCOM'95.

[22]  Hanseok Ko,et al.  A threshold based scheduling algorithm for input queue switch , 2001, Proceedings 15th International Conference on Information Networking.

[23]  Cheng-Shang Chang,et al.  Load balanced Birkhoff-von Neumann switches , 2001, 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552).

[24]  Nick McKeown,et al.  A Starvation-free Algorithm For Achieving 100% Throughput in an Input- Queued Switch , 1999 .

[25]  Satoshi Nojima,et al.  Integrated Services Packet Network Using Bus Matrix Switch , 1987, IEEE J. Sel. Areas Commun..

[26]  Naoaki Yamanaka,et al.  High-speed ATM switch with input and cross-point buffers , 1993 .

[27]  Tara Javidi,et al.  A high-throughput scheduling algorithm for a buffered crossbar switch fabric , 2001, ICC 2001. IEEE International Conference on Communications. Conference Record (Cat. No.01CH37240).

[28]  Y. Tamir,et al.  High-performance multi-queue buffers for VLSI communications switches , 1988, ISCA '88.

[29]  Marco Ajmone Marsan,et al.  Packet scheduling in input-queued cell-based switches , 2001, Proceedings IEEE INFOCOM 2001. Conference on Computer Communications. Twentieth Annual Joint Conference of the IEEE Computer and Communications Society (Cat. No.01CH37213).

[30]  Yuval Tamir,et al.  High-performance multiqueue buffers for VLSI communication switches , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

[31]  Samuel P. Morgan,et al.  Input Versus Output Queueing on a Space-Division Packet Switch , 1987, IEEE Trans. Commun..

[32]  R. Rojas-Cessa,et al.  CIXB-1: combined input-one-cell-crosspoint buffered switch , 2001, 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No.01TH8552).