Writing correct and usable specifications for board and test: a case study

The author notes that current board test system specifications are not adequate for a complete analysis of tester capability. He examines the error sources in timing specification; defines overall edge placement accuracy; discusses automatic compensation techniques for a distributed architecture tester; shows the effect of load, slew rate, and level variations on specifications; and gives techniques to verify manufacturer's claims. He demonstrates that, in order to be meaningful, a driver or receiver must be referenced to other drivers and receivers, to an internal tester clock, and, ideally, to a user-supplied reference clock. It is concluded that, although the overall edge placement accuracy specification is extremely useful, the user needs to recognize how limitations, such as variations in loads, programmed levels, and programmed slew rates, will affect the edge placement accuracy of the tester.<<ETX>>

[1]  Jay M. Stepleton.  A new system architecture for a combined in-circuit/functional tester , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[2]  Kenneth P. Parker.  Integrating design and test : using CAE tools for ATE programming , 1987 .

[3]  Richard Swan,et al.  Individual Signal Path Calibration for Maximum Timing Accuracy in a High Pincount VLSI Test System , 1983, ITC.

[4]  Phillip N. King.  Flexible, high-performance pin electronics implementation , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[5]  Kenji Yoshida,et al.  Analysis and Definition of Overall Timing Accuracy in VLSI Test System , 1981, ITC.

[6]  John Arena.  Evaluating the limitations of high-speed board testers , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.