Power Distribution in TSV-Based 3-D Processor-Memory Stacks

Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle, and via-last, have been analyzed and compared to distribute power in a 3-D processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this paper. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a 3-D power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to the number of TSVs and decoupling capacitance.

[1]  B. Dang,et al.  3D chip stack with integrated decoupling capacitors , 2009, 2009 59th Electronic Components and Technology Conference.

[2]  Sung Kyu Lim,et al.  Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs , 2009, SLIP '09.

[3]  E. Friedman,et al.  Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance , 2009, IEEE Transactions on Electron Devices.

[4]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[5]  Gang Huang,et al.  Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication , 2007, 2007 IEEE Electrical Performance of Electronic Packaging.

[6]  Soha Hassoun,et al.  Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  J. W. Elam,et al.  Surface chemistry and film growth during TiN atomic layer deposition 4 using TDMAT and NH 3 , 2022 .

[8]  Pingqiang Zhou,et al.  Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity , 2009, IEEE Design & Test of Computers.

[9]  Emre Salman,et al.  Substrate and Ground Noise Interactions in Mixed-Signal Circuits , 2006, 2006 IEEE International SOC Conference.

[10]  Arvind Kumar,et al.  Three-dimensional integrated circuits , 2006, IBM J. Res. Dev..

[11]  S. Pamarthy,et al.  Process Integration Considerations for 300 mm TSV Manufacturing , 2009, IEEE Transactions on Device and Materials Reliability.

[12]  R. Anciant,et al.  Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results , 2009, 2009 11th Electronics Packaging Technology Conference.

[13]  X. Baillin,et al.  Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon , 2007, 2007 Proceedings 57th Electronic Components and Technology Conference.

[14]  Ajay Agarwal,et al.  Polysilicon interconnections (FEOL): Fabrication and characterization , 2009, 2009 11th Electronics Packaging Technology Conference.

[15]  Emre Salman,et al.  Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  Jian-Qiang Lu,et al.  3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems , 2009, Proceedings of the IEEE.

[17]  Tong Zhang,et al.  3-D Data Storage, Power Delivery, and RF/Optical Transceiver—Case Studies of 3-D Integration From System Design Perspectives , 2009, Proceedings of the IEEE.

[18]  K. Soejima,et al.  A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer , 2006, 2006 International Electron Devices Meeting.

[19]  Gang Huang,et al.  Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[20]  Sally A. McKee,et al.  Hitting the memory wall: implications of the obvious , 1995, CARN.

[21]  C.K. Chen,et al.  A wafer-scale 3-D circuit integration technology , 2006, IEEE Transactions on Electron Devices.

[22]  R. Tatikola,et al.  Simulation study of power delivery performance on flip-chip substrate technologies , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[23]  Aamir Zia,et al.  Mitigating Memory Wall Effects in High-Clock-Rate and Multicore CMOS 3-D Processor Memory Stacks , 2009, Proceedings of the IEEE.

[24]  Giovanni De Micheli,et al.  Power distribution paths in 3-D ICS , 2009, GLSVLSI '09.

[25]  Thuy Dao,et al.  Thermo-mechanical stress characterization of tungsten-fill through-silicon-via , 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

[26]  Emre Salman,et al.  High Performance Integrated Circuit Design , 2012 .

[27]  Mitsumasa Koyanagi,et al.  Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs , 2008 .

[28]  C. Laviron,et al.  Via first approach optimisation for Through Silicon Via applications , 2009, 2009 59th Electronic Components and Technology Conference.

[29]  Nanning Zheng,et al.  3D DRAM Design and Application to 3D Multicore Systems , 2009, IEEE Design & Test of Computers.

[30]  Pingqiang Zhou,et al.  Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors , 2009, 2009 Asia and South Pacific Design Automation Conference.

[31]  Tong Zhang,et al.  Design Techniques to Facilitate Processor Power Delivery in 3-D Processor-DRAM Integrated Systems , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[32]  Mark Y. Liu,et al.  A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array , 2008, 2008 IEEE International Electron Devices Meeting.

[33]  Joungho Kim,et al.  TSV modeling and noise coupling in 3D IC , 2010, 3rd Electronics System Integration Technology Conference ESTC.

[34]  W. Dehaene,et al.  Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs , 2010, IEEE Transactions on Electron Devices.

[35]  M. Kawano,et al.  Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer , 2008, IEEE Transactions on Electron Devices.

[36]  TingTing Hwang,et al.  TSV Redundancy: Architecture and Design Issues in 3-D IC , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[37]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について － , 2004 .

[38]  Katsuyuki Sakuma,et al.  Three-dimensional silicon integration , 2008, IBM J. Res. Dev..

[39]  S. Ramaswami,et al.  Robust TSV via-middle and via-reveal process integration accomplished through characterization and management of sources of variation , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[40]  Kaustav Banerjee,et al.  3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.

[41]  Taigon Song,et al.  PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[42]  Muhannad S. Bakir,et al.  Integrated Interconnect Technologies for 3D Nanoelectronic Systems , 2008 .

[43]  Steven M. George,et al.  Surface chemistry and film growth during TiN atomic layer deposition using TDMAT and NH3 , 2003 .

[44]  P. Brianceau,et al.  Through Silicon Via technology using tungsten metallization , 2011, 2011 IEEE International Conference on IC Design & Technology.

[45]  Emre Salman,et al.  Signal integrity analysis of a 2-D and 3-D integrated potentiostat for neurotransmitter sensing , 2011, 2011 IEEE Biomedical Circuits and Systems Conference (BioCAS).

[46]  Shekhar Y. Borkar.  3D integration for energy efficient system design , 2006, 2009 Symposium on VLSI Technology.