Automated FSM Error Correction for Single Event Upsets

This paper presents a technique for automatic error correction of finite state machines (FSMs) from single event upsets (SEUs). We present a general technique of adding Hamming errorchecking bits to automatically recover from single-bit errors within the same clock cycle. Experimental results on field programmable gate array (FPGA) devices demonstrate the efficacy of the method.

[1]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[2]  Régis Leveugle,et al.  Analysis and comparison of fault tolerant FSM architecture based on SEC codes , 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[3]  Donatella Sciuto,et al.  A state encoding for self-checking finite state machines , 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

[4]  D. B. Armstrong.  A general method of applying error correction to synchronous digital systems , 1961 .

[5]  Regis Leveugle,et al.  Design methodology of FSMs with intrinsic fault tolerance and recovery capabilities , 1992, Proceedings Euro ASIC '92.

[6]  Régis Leveugle.  Optimized State Assignment of Single Fault Tolerant FSMs Based on SEC Codes , 1993, 30th ACM/IEEE Design Automation Conference.

[7]  John F. Meyer,et al.  Fault Tolerant Sequential Machines , 1971, IEEE Transactions on Computers.

[8]  Paul Pinella,et al.  Mentor Graphics Corp. , 1993 .