MsBV: A Memory Compression Scheme for Bit-Vector-Based Classification Lookup Tables

Packet classification is widely used in Software-Defined Networking (SDN). At present, packet classification is mainly implemented by software, such as OpenvSwitch, which has the disadvantage of low performance. On the Field Programmable Gate Array (FPGA) platform, FPGA has the advantages of reconfigurability and high processing performance. The current work proposes the FPGA-based Bit-Vector algorithms in packet classification, which has the advantages of determining latency and high throughput. In the Bit-Vector-based algorithms, stringent memory resources in FPGA are wasted to store relatively useless wildcards because there are plenty of wildcards in the rules. A bit-vector-based memory compression scheme named Memory-shared Bit-Vector (MsBV) is proposed. MsBV adopts a memory-shared homogeneous two-dimensional pipeline architecture, and it can reduce memory consumption and ensure the correctness of packet classification. In MsBV, we reduce memory consumption better by rearranging the bit matrix. The experimental results show that MsBV saves about 43.69% memory resources, 57.53% the number of ALUTs, and 37.59% the number of Registers compared to StrideBV of 100K OpenFlow rules.

[1]  Patrick Th. Eugster,et al.  SAX-PAC (Scalable And eXpressive PAcket Classification) , 2014, SIGCOMM.

[2]  Viktor K. Prasanna,et al.  A Scalable and Modular Architecture for High-Performance Packet Classification , 2014, IEEE Transactions on Parallel and Distributed Systems.

[3]  Pankaj Gupta,et al.  Packet Classification using Hierarchical Intelligent Cuttings , 1999 .

[4]  Kushagra Vaid,et al.  Azure Accelerated Networking: SmartNICs in the Public Cloud , 2018, NSDI.

[5]  Suman Banerjee,et al.  A smart pre-classifier to reduce power consumption of TCAMs for multi-dimensional packet classification , 2012, SIGCOMM '12.

[6]  Tao Li,et al.  FAS: Using FPGA to Accelerate and Secure SDN Software Switches , 2018, Secur. Commun. Networks.

[7]  Martín Casado,et al.  The Design and Implementation of Open vSwitch , 2015, NSDI.

[8]  Xiang Wang,et al.  ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification , 2012, 2012 IEEE 20th Annual Symposium on High-Performance Interconnects.

[9]  Xianfeng Li,et al.  CutSplit: A Decision-Tree Combining Cutting and Splitting for Scalable Packet Classification , 2018, IEEE INFOCOM 2018 - IEEE Conference on Computer Communications.

[10]  Jonathan S. Turner,et al.  ClassBench: A Packet Classification Benchmark , 2005, IEEE/ACM Transactions on Networking.

[11]  Anand Rangarajan,et al.  Algorithms for advanced packet classification with ternary CAMs , 2005, SIGCOMM '05.

[12]  Gaogang Xie,et al.  Meta-algorithms for Software-Based Packet Classification , 2014, 2014 IEEE 22nd International Conference on Network Protocols.

[13]  Xianfeng Li,et al.  HybridCuts: A Scheme Combining Decomposition and Cutting for Packet Classification , 2013, 2013 IEEE 21st Annual Symposium on High-Performance Interconnects.

[14]  Nick McKeown,et al.  OpenFlow: enabling innovation in campus networks , 2008, CCRV.

[15]  Viktor K. Prasanna,et al.  Field-split parallel architecture for high performance multi-match packet classification using FPGAs , 2009, SPAA '09.

[16]  Venkatachary Srinivasan,et al.  Packet classification using tuple space search , 1999, SIGCOMM '99.

[17]  T. V. Lakshman,et al.  High-speed policy-based packet forwarding using efficient multi-dimensional range matching , 1998, SIGCOMM '98.

[18]  George Varghese,et al.  Packet classification using multidimensional cutting , 2003, SIGCOMM '03.

[19]  Hui Yang,et al.  Memory Optimization for Bit-Vector-Based Packet Classification on FPGA , 2019, Electronics.

[20]  Jirí Matousek,et al.  ClassBench-ng: Recasting ClassBench after a Decade of Network Evolution , 2017, 2017 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).

[21]  Tao Li,et al.  Design and implementation of Software Defined Hardware Counters for SDN , 2016, Comput. Networks.

[22]  Eric Torng,et al.  TupleMerge: Building Online Packet Classifiers by Omitting Bits , 2017, 2017 26th International Conference on Computer Communication and Networks (ICCCN).

[23]  Yongqiang Xiong,et al.  ClickNP: Highly Flexible and High Performance Network Processing with Reconfigurable Hardware , 2016, SIGCOMM.

[24]  Baohua Yang,et al.  Packet Classification Algorithms: From Theory to Practice , 2009, IEEE INFOCOM 2009.

[25]  T. N. Vijaykumar,et al.  EffiCuts: optimizing packet classification for memory and throughput , 2010, SIGCOMM '10.

[26]  Viktor K. Prasanna,et al.  High-Performance and Dynamically Updatable Packet Classification Engine on FPGA , 2016, IEEE Transactions on Parallel and Distributed Systems.